Storage Technology Corporation

Robert J Moreno

P David Dodd

Ronald L Blickenstaff

Richard L Coulson

Brian E Trede

Dean P Kinard

Robert W Schmidt

A solid-state cache memory subsystem configured to be used in conjunction with disk drives for prestaging of data in advance of its being called for by a host computer features a controller featuring means for establishing and maintaining precise correspondence between storage locations in the solid-state array and on the disk memory, for use in establishing a reoriented position on a disk in the event of error detection, and in order to determine when a predetermined quantity of data has been read from the disk into the cache in a staging operation.

Control of cache buffer for memory subsystem

A method for detection of a sequential data stream which can be performed in a data storge subsystem without host computer intervention is disclosed featuring examination of the channel program processed during a read operation for signals indicative that the data is not part of a sequential data stream, for example, embedded seek instructions. If a particular channel program for does not contain such indications, the successive record or records may then be staged to a faster access memory device such as a solid-state cache. The invention is described in a plug-compatible, software-transparent configuration.

Detection of sequential data stream

A method of operation of a memory array for storage of records of differing predetermined sizes is disclosed which features division of the array into domains which are substantially integral multiples of the predetermined record sizes. In a preferred embodiment the domain allocation may be varied adaptively in accordance with usage so as to enable more efficient use of the array.

Adaptive domain partitioning of cache memory space

A method for detection of a sequential data stream which can be performed without host computer intervention is disclosed featuring examination of a data record and channel program during read operations for signals indicative that the data is not part of a sequential data stream, for example, embedded seek instructions. If a particular sought for record does not contain such indications, the successive record or records may then be staged to a faster access memory device such as a solid-state cache. The invention is described in a plug-compatible, software-transparent configuration.

Detection of sequential data stream for improvements in cache data

A method of operation of a memory array for storage of records of differing predetermined sizes is disclosed which features division of the array into domains which are substantially integral multiples of the predetermined record sizes. In a preferred embodiment the domain allocation may be varied adaptively in accordance with usage so as to enable more fully efficient use of the array.

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Boulder, CO, United States of America

Robert J Moreno