International Rectifier Corporation

Infineon Technologies Americas Corp.

Robert J Montgomery

David Paul Jones

Hugo R Burke

Susan Johns

Jianjun Cao

Kyle A Spring

Hugo R G Burke

Paul Harvey

Florian Bieck

Philip Parsonage

Ling Ma

Rupert Burbidge

David Kent

Amarjit Dhadda

Phillip Parsonage

Dave Kent

In one implementation, a method for forming ultra-thin semiconductor components includes fabricating multiple devices including a first device and a second device in a semiconductor wafer, and forming a street trench within the semiconductor wafer and between the first and second devices. The method continues with forming a dielectric skeleton structure over the semiconductor wafer, the dielectric skeleton structure laterally extending to at least partially cover the first and second devices, while also substantially filling the street trench. The method continues with thinning the semiconductor wafer from a backside to expose the dielectric skeleton structure in the street trench to form a first ultra-thin semiconductor component having the first device, and a second ultra-thin semiconductor component having the second device. The method can conclude with cutting through the dielectric skeleton structure to singulate the first and second ultra-thin semiconductor components.

Ultra-thin semiconductor component fabrication using a dielectric skeleton structure

A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.

Power semiconductor device with a double metal contact and related method

Power semiconductor device with a double metal contact

The present disclosure includes novel techniques to provide wafer level fan-outs in electronic circuit packages housing one or more circuit devices, at least one of which has input and/or output nodes disposed on opposite facings.

Packaging of electronic circuitry

An assembler receives a circuit device and a mass of conductive material such as a diode, metal material, etc. The assembler bonds a first facing of a circuit device to a substrate. Adjacent to the circuit device, the assembler bonds a first facing of the mass of conductive material to the substrate. The assembler applies an overmold layer of insulation material over the substrate adjacent the circuit device and the mass of conductive material. Subsequent to applying the overmold layer of insulation material, the assembler provides a conductive link between a second facing of the circuit device and a second facing of the mass of conductive material.

According to one embodiment, a semiconductor wafer comprises a plurality of solder bumps for providing device contacts formed over a functional region of the semiconductor wafer, and one or more support rings surrounding the functional region. The one or more support rings and the plurality of solder bumps are formed so as to have substantially matching heights. The presence of the one or more support rings causes the semiconductor wafer to have a substantially uniform thickness in the functional region after a thinning process is performed on the semiconductor wafer. A method for fabricating the semiconductor wafer comprises forming the plurality of solder bumps over the functional region, and forming the one or more support rings surrounding the functional region before performing the thinning process on the semiconductor wafer.

Semiconductor wafer with reduced thickness variation and method for fabricating same

Power semiconductor device including a double metal contact

A support tape used in semiconductor wafer processing that includes an adhesive tape and a plurality of spaced support ribs arranged on the adhesive tape.

Peelable tape carrier

A method of singulating a semiconductor die from a wafer is provided. The method includes etching or cutting several trenches into the wafer from a front surface of the wafer, such that each trench extends along an entire side of the die; depositing a passivation layer into the trenches to form a passivation plug on at least a bottom of the trenches to protect the dies and immobilize them during singulation; and forming a rigid carrier layer or plate at the first side of the wafer to secure the dies. The wafer is then ground from the back side to expose the bottom of each trench, a metal layer is formed on the back surface of the wafer; dicing tape is added, the carrier layer is removed, and the die is separated from the wafer by laser cutting or by flexing the tape.

Wafer singulation process

A trench type power semiconductor device which includes deposited rather than grown oxide in the trenches for the electrical isolation of electrodes disposed inside the trenches from the semiconductor body.

Trench MOSFET with deposited oxide

A laser ablated wafer for a semiconductor device, such as a MOSFET or other power device, and a method of producing such a wafer to achieve a lower electrical resistance are provided. The method includes forming first holes, slots or trenches on a first surface of the wafer and focusing a laser beam to form second trenches on a bottom surface of the wafer, and filling the trenches, for example using aluminum or other metallic filling, to provide conductive electrodes or conductive surfaces for the semiconductor device. In such a wafer each trench on the second surface may be deeper, for example more than one hundred microns deep and tens of microns wide.

[object Object]

A semiconductor package that includes at least two semiconductor devices that are coupled to one another through a conductive clip.

Semiconductor package that includes stacked semiconductor die

A power semiconductor device which includes gate liners extending along gate insulation liners and an insulation block spacing the two gate liners.

Split electrode gate trench power device

A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are formed in the semiconductor body along the trench edges and are then driven. Insulation caps are then formed over the trenches. Outside spacers are next formed along the sides of the caps. Using these spacers as masks, the semiconductor surface is etched and high conductivity contact regions formed. The outside spacers are then removed and source and drain contacts formed. Alternatively, the source implants are not driven. Rather, prior to outside spacer formation a second source implant is performed. The outside spacers are then formed, portions of the second source implant etched, any remaining source implant driven, and the contact regions formed. The gate electrodes are either recessed below or extend above the semiconductor surface.

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Marshfield Cardiff, United Kingdom

Robert J Montgomery