Hughes Aircraft Company

Other

Robert J McMillen

Andrew Rosman

Norton L Moise

Chao Yang

Gary N Landis

Myron L Nack

Thomas O Ellis

A system using a ray-tracing algorithm and a hierarchy of volume elements (called voxels) to process only the visible surfaces in a field of view. In this arrangement, a dense, three-dimensional voxel data base is developed from the objects, their shadows and other features recorded, for example, in two-dimensional aerial photography. The rays are grouped into subimages and the subimages are executed as parallel tasks on a multiple instruction stream and multiple data stream computer (MIMD). The use of a three-dimensional voxel data base formed by combining three-dimensional digital terrain elevation data with two-dimensional plan view and oblique view aerial photography permits the development of a realistic and cost-effective data base. Hidden surfaces are not processed. By processing only visible surfaces, displays can now be produced depicting the nap-of-the-earth as seen in low flight of aircraft or as viewed from ground vehicles. The approach employed here is a highly-parallel data processing system solution to the nap-of-the-earth flight simulation through a high level of detail data base. The components of the system are the display algorithm and data structure, the software which implements the algorithm and data structure and creates the data base, and the hardware which executes the software. The algorithm processes only visible surfaces so that the occulting overload management problem is eliminated at the design level. The algorithm decomposes the image into subimages and processes the subimages independently.

Digital visual and sensor simulation system for generating realistic

A packet switching node which processes applied data packets containing routing tag signals indicative of the output port destination to which the data packets are to be applied. The invention comprises an N.times.M switch node that accepts data packets at any of N input ports and routes each to any of M output ports. The output selected is determined by the routing tag signal in the packet. The node comprises a multiport memory having a predetermined number of memory locations available for storage of data packets applied to each of a plurality of input ports. Control logic coupled to the input and output ports and memory is designed so that the data packets are effectively sorted according to their desired output port destination. The control logic comprises arbitration logic which randomly, in a statistical sense, chooses among any data packets that are directed to the same output port. The algorithm implemented by the arbitration logic is designed so that data packets will not wait indefinitely to be routed from the switch node. A method in accordance with the present invention comprises sorting and storing the data packets based upon the output port destination and then arbitrating among the data packets. The final step involves routing the data packets selected during the arbitration processes to the output ports identified in the routing tag signals.

Packet switched multiport memory NXM switch node and processing method

A packet switching node which processes data packets containing routing tag signals indicative of the output port destination thereof and which routes these data packets to the specified output ports. A plurality of queue selectors are individually coupled between a plurality of input ports and a plurality of queue sets that comprise a plurality of queues which store and forward data packets applied thereto as a function of output port destination. Each of the plurality of queue selectors sort the data packets applied thereto in accordance with the output port destination thereof. The queues of each queue sets are coupled to different output arbitrators which control routing to a particular output port. The packet switching node eliminates the problem of contention between data packets arriving at an input port of the node whose destinations are different output ports. The packet switching node sorts applied data packets according to output port destination to reduce contention and hence has improved performance and higher throughput. The present invention also contemplates a method of processing applied data packets containing routing tag signals indicative of the output port destinations to which the data packets are to be applied. The method comprises sorting and storing the data packets in accordance with the routing tag signals, arbitrating among data packets that have been stored that contend for the same output port, and then routing the selected data packet to the output port identified in the routing tag signal.

Packet switched multiple queue NXM switch node and processing method

A load balancing circuit arrangement for use with a packet switching node. The packet switching node processes applied data packets containing routing tag signals indicative of the output port destinations to which the data packets are addressed, and routes these packets to the identified output ports. The present invention a load balancing circuit coupled to the packet switching node which monitors the output port addresses of the applied data packets and monitors the number of data packets addressed to each of the output ports. The load balancing circuit is adapted to generate new routing tag signals identifying output port addresses which redistribute the output port load. The load balancing circuit arrangement includes a tag selection circuit coupled to the load balancing circuit and the packet switching node which selectively replaces the routing tag signals of the applied data packets with the new routing tage signals in order to redistribute and balance the output port load. The load balancing circuit comprises a minimum index circuit for generating the new routing tag signals and an adder circuit coupled thereto. The minimum index circuit combines the new routing tag signals with offset signals that modify the new routing tag signals in order to implement a predetermined output port priority scheme. The load balancing circuit arrangement may be employed in both multiple queue and multiport memory packet switching nodes employed in computer or telephone communications applications.

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Long Beach, CA, United States of America

Robert J McMillen