Quickturn Design Systems, Inc.

Robert J Ko

Thomas B Huang

Ming-Yang Wang

Jeong-Tyng Li

Nang-Ping Chen

A method and a structure provide emulation circuit implemented on a logic block module comprising clocked and unclocked field programmable logic devices (FPGAs). Software modules analyze the target logic circuit and impose delay constraints to require certain storage instances to be implemented on separate FPGAs so as to prevent hold time violation artifacts.

Structure and method for providing reconfigurable emulation circuit

A method and a structure for implementing integrated circuit designs into a plurality of clocked and unclocked reprogrammable logic circuits. Software structures analyze the target logic circuit, form clusters, partitions the integrated circuit design and implement the partitions into the clocked and unclocked reprogrammable logic circuits in order to prevent hold time violation artifacts.

Methods for controlling timing in a logic emulation system

A method and a structure for implementing integrated circuit designs into a plurality of clocked and unclocked reprogrammable logic circuits. Software structures analyze the target logic circuit, form clusters, partition the integrated circuit design and implement the partitions into the clocked and unclocked reprogrammable logic circuits in order to prevent hold time violation artifacts.

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Saratoga, CA, United States of America

Robert J Ko