Xilinx, Inc.

Rosemount Inc.

Robert J Kaszynski

Charles Edwin Goetzinger

An assembly includes a thermocouple, a cold junction sensor, and a circuit. The thermocouple has a process end and a cold junction end. The cold junction end has first and second cold junction terminals. The cold junction sensor is supported near the cold junction end and configured to measure temperature at the cold junction end. The circuit is electrically connected to the cold junction sensor and to the first and second cold junction terminals. The circuit is configured to produce a thermocouple signal as a function of voltage across the first and second cold junction terminals and to produce a cold junction sensor signal as a function of temperature of the cold junction end as measured by the cold junction sensor. The circuit is further configured to calculate a correlation between the thermocouple signal and the cold junction sensor signal.

Thermocouple temperature sensor with connection detection circuitry

A method for providing placement based configurations in integrated circuits and integrated circuits having configurable data files for logic blocks based on the location of the blocks therein are disclosed. Location information for at least one logic block in an integrated circuit is identified. A configuration data file for configuring the at least one logic block in the integrated circuit is generated based on the identified location of the at least one logic block.

Method and system for providing placement based configurations in integrated circuits

A method and apparatus for providing channel bonding and clock correction arbitration in integrated circuits are disclosed. An arbitration device analyzes indicators to determine when clock correction request or a channel bonding request occur simultaneously. Then, the arbitration device determines whether to service the simultaneously occurring clock correction request first or a channel bonding request first based upon user selected arbitration logic.

Method and apparatus for providing channel bonding and clock correction arbitration

A method, apparatus and program storage device for modeling an analog PLL for use in a digital simulator are disclosed. A model of a phase locked loop to be simulated in a digital simulator includes a behavioral model for simulating a phase locked loop as a set of behavioral blocks based upon a high level description language and a loop filter model, used by the behavioral model, the loop filter model being implemented as a series of integrators based on a transfer function for creating a loop voltage for generating phase adjustments. The PLL behavior is based on actual circuit parameters and produces accurate behavior in a fraction of the time required using an analog simulator.

Method, apparatus and program storage device for modeling an analog PLL for use in a digital simulator

A method for providing placement based configurations in programmable logic devices and programmable logic devices having configurable data files for logic blocks based on the location of the blocks therein are disclosed. Location information for at least one logic block in a programmable logic device is identified. A configuration data file for configuring the at least one logic block in the programmable logic device is generated based on the identified location of the at least one logic block.

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Mendota Heights, MN, United States of America

Robert J Kaszynski