Motorola Corporation

Freescale Semiconductor,inc.

Robert J Johnsen

Paul W Sanders

Robert A Pryor

John L Freeman, Jr

Raymond J Balda

Robert Bruce Davies

Francine Y Robb

James D Paulsen

Joseph L Petrucci, Jr

In a semiconductor manufacturing method, an emitter region () and a base enhancement region () are formed to provide linear voltage, capacitance and low resistance characteristics. In the manufacturing method, a semiconductor device () is formed on a silicon substrate layer () with an epitaxial layer (). Trenches () are cut into the epitaxial layer () and filled with oxide () to provide reduced junction capacitance and reduced base resistance. The emitter region () and the base enhancement region () are simultaneously formed through an anneal process.

Semiconductor device and method of manufacture

A method of manufacturing a semiconductor component includes providing a composite substrate ( ) with a dielectric portion and a semiconductor portion and growing an epitaxial layer ( ) over the composite substrate. The epitaxial layer has a polycrystalline portion ( ) over the dielectric portion of the composite substrate and also has a monocrystalline portion ( ) over the semiconductor portion of the composite substrate. A first dopant is diffused into the monocrystalline portion of the epitaxial layer to form an emitter region in the monocrystalline portion of the epitaxial layer while a second dopant is simultaneously diffused into the monocrystalline portion of the epitaxial layer to form an enhanced portion of the base region.

Method of manufacturing a semiconductor component

A semiconductor device having a low source inductance are fabricated by having a maximum of two sources each in contact with a region which makes contact to a substrate or back side of the device. The back side source contact also allows the device to be mounted directly to a grounded heatsink.

Semiconductor device having low source inductance

A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N.sup.+, N-, P-, N.sup.+ regions arranged between top and bottom surfaces of the semiconductor die. In a preferred implementation, two trenches are etched from the top surface to the P-, N.sup.+ interface. A buried P-, N.sup.+ short is provided in one trench and a gate dielectric and gate electrode are provided over the sidewall P- region exposed in the other trench. This creates a vertical MOSFET in which the N.sup.+ substrate forms the source region shorted to the P- body region in which the channel is created by the gate. Superior performance is obtained in RF grounded-source circuit applications.

MOSFET with substrate source contact

A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N.sup.+, N-,P-, N.sup.+ regions arranged between top and bottom surfaces of the semiconductor die. In a preferred implementation, two trenches are etched from the top surface to the P-, N.sup.+ interface. A buried P-, N.sup.+ short is provided in one trench and a gate dielectric and gate electrode are provided over the sidewall P- region exposed in the other trench. This creates a vertical MOSFET in which the N.sup.+ substrate forms the source region shorted to the P- body region in which the channel is created by the gate. Superior performance is obtained in RF grounded-source circuit applications.

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Scottsdale, AZ, United States of America

Robert J Johnsen