Tektronix, Inc.

Robert J Heath

Michael S Hagen

Jonathan D Clem

James M Fenton

Glenn R Johnson

Kenneth R Marti

David L Bennett

Mark L Millard

A method of trace delay error compensation for measurements that are taken remotely from the signal source or receiver of a circuit uses data available from a computer aided design (CAD) tool to characterize electrical connections to an instrument measurement point, such as a connectorless probe, which is remote from the signal source or receiver. Extracted parameters from the CAD data are applied to signals acquired by the probe to adjust the signal timing and/or shape to more accurately represent the signal information timing at the signal source or receiver or other remote location of interest to a user. The corrected signals at the desired location may be displayed by a measurement instrument.

Trace delay error compensation

Apparatus according to the subject invention includes two independent acquisition systems, wherein one of the two independent acquisition systems acquires the acquisition clock of the other acquisition system along with a signal from a known acquisition reference point. In general, the first independent acquisition system is a logic analyzer, and the second independent acquisition system can be an ILA, a second logic analyzer, an oscilloscope, or other sampling device.

Time correlation of data acquisition samples from independent systems in a logic analyzer

A logic analyzer according to the subject invention includes a disassembler for disassembling object code. The disassembler automates the process of locating op-code addresses by utilizing information derived from an object file corresponding to the code whose execution is being disassembled. The object file includes addresses for the starting location of op-codes corresponding to individual source code lines. When the disassembler cannot determine the correct starting location for an op-code, it uses information from the object file to obtain the address of an op-code within a specified range of interest.

Logic analyzer having a disassembler employing symbol table information for identifying op-codes

A system and method for locating a data sample in a logic analyzer or emulator acquisition buffer corresponding to a source code statement employs first and second windows, wherein one window displays the contents of the acquisition buffer, for example, in disassembly form and the other window displays source code. When a source code file is displayed and a specified statement is selected within the source code, a search for a matching sample in the acquisition buffer is initiated. If a sample is found, it is displayed and highlighted in the appropriate window.

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Aloha, OR, United States of America

Robert J Heath