Nvidia Corporation

Robert J Hasslen

Sean Jeffrey Treichler

Karim Abdalla

Jonah Matthew Alben

Samuel Hammond Duncan

Robert Anthony Alfieri

Paolo Enrique Sabella

Craig Michael Wittenbrink

Christopher James Goodman

Lincoln G Garlick

Thomas Melvin Ogletree

Scott R Whitman

Abdulkadir Utku Diril

Hungse Cha

John A Robinson

Miodrag Vujkovic

Anish Muttreja

Kaushal Rajendra Gandhi

A technique for determining thermal design point (TDP) power efficiency for an integrated circuit is disclosed. A simulation executes a set of input vectors on a model of an integrated circuit to generate a first estimated power consumption data during a first number of clock cycles. A simulation executes the set of input vectors on a model of an integrated circuit to generate a second estimated power consumption data during a second number of clock cycles. TDP power efficiency for the integrated circuit is calculated based on the first estimated power consumption data and the second estimated power consumption data.

Flow and methodology to find TDP power efficiency

A power monitor for electronic devices, such as computer chips, is used to estimate the power consumption and to compare the estimated power consumption against the power budget. The estimated power consumption is based on activity signals from various functional blocks of the computer chip. The activity signals that are monitored correlate accurately to the total number of flip-flops that are active at a given time. If the estimated power consumption exceeds the power budget, the speed of the clock signals supplied to the computer chip is reduced.

Power estimation based on block activity

An embodiment of the invention includes receiving an indicator of an activity-level of a functional block within an electronic chip. The functional block is configured to receive a clock signal from a clock signal generator. The clock signal to at least a portion of a functional block is disabled for a number of inactive clock cycles during a clock segment of the clock signal. The clock segment has a specified number of clock cycles and the number of inactive clock cycles is defined based on the activity-level and the specified number of clock cycles of the clock segment.

Clock throttling based on activity-level signals

Generally, the present disclosure concerns systems and methods for shadowing status for a circuit with a shadow unit. In one aspect, a system comprises a first circuit in a first dynamic clock domain of a plurality of dynamic clock domains, a processor configured to execute software instructions to generate a request for a status of the first circuit, and a second circuit coupled to the first circuit and to the processor. The second circuit, outside the first dynamic clock domain, is configured to shadow a status of the first circuit and to respond to the request for the status of the first circuit with the shadowed status.

Shadow unit for shadowing circuit status

An embodiment of the invention includes receiving an indicator of a flow of data associated with a graphics processing stage within a graphics pipeline of a graphics processor. A clock signal to a portion of the graphics processing stage is modified based on a status of the flow of data. The clock signal is received from a clock signal generator within the graphics processor.

Functional block level clock-gating within a graphics processor

An embodiment of the invention includes receiving an indicator of an activity-level of a functional block within an electronic chip. The functional block is included in a processing pipeline having a plurality of functional blocks. Each functional block from the plurality is configured to receive a clock signal from a clock signal generator. A status of the functional block is determined based on the activity-level. The clock signal to at least a portion of the functional block is disabled when the status is an inactive status.

Automatic functional block level clock-gating

Systems and methods for monitoring the accuracy of unit status reporting within an application specific integrated circuit device may be used reduce power consumption. Accurate status reporting of an idle state is needed to safely disable a clock signal for a unit in order to reduce the power needed by that unit. A watchdog monitor may be used during functional simulation and synthesized for formal verification, emulation, and functional device testing and debugging. The watchdog monitor may also be configured based on specific characteristics of the unit that it is monitoring.

Watchdog monitoring for unit status reporting

Graphics processing devices and methods are provided for culling small primitives that do not cover any pixels. A boundary (e.g., a diamond) is defined around a pixel center, with pixel coverage being determined for some types of primitives based on whether the boundary is crossed. The boundaries divide the raster into internal regions and external regions. Each region is assigned a unique canonical identifier. Each vertex of a primitive is assigned the canonical identifier corresponding to the region that contains that vertex. The canonical coordinates of the vertices are used to cull primitives that do not satisfy the boundary crossing coverage rules for any pixels.

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Menlo Park, CA, United States of America

Robert J Hasslen