Intel Corporation

Other

Robert J Greiner

Edward Allyn Burton

Anant S Deval

Stephen H Gunther

Stephan Jourdan

David W Grawrock

Ioannis T Schoinas

Linda J Rankin

Kushagra V Vaid

Michael Cornaby

John H Wilson

Mazin S Yousif

James A Sutton, Ii

Willard M Wiseman

David Lawrence Hill

Douglas Robert Huard

Stephen S Pawlowski

Gurbir Singh

Donald D Parker

Kevin Dai

Matthew M Ma

Keng L Wong

Hung-Piao Ma

Benson D Inkley

Nasser A Kurd

Jeremy J Shrall

Derek T Bachand

Keshavan K Tiruvallur

Doug Huard

Alon Naveh

Shreekant S Thakkar

Chee How Lim

Frank Binns

Herbert H J Hum

Greg F Taylor

Roman Surgutchik

Songmin Kim

Peter J Ruscito

Madhavan Parthasarathy

Pranav H Mehta

Hong-Piao Ma

Mark R Waggoner

Arun R Ramadorai

Nathan C Schultz

Martin M Chang

Ying Cole

Robert G Blankenship

David I Poisner

Per H Hammarlund

Jasmin Ajanovic

Kenneth C Creta

Lily Pao Looi

Matthew A Fisch

Tim Frodsham

Douglas M Carmean

Rupin H Vakharwala

Rajesh S Parthasarathy

Xia Dai

Raymond Scott Tetrick

Sham M Datta

Jeff C Morriss

Edward Paul Osburn

Mark L Neidengard

Chinna B Prudvi

Vaughn J Grossnickle

James A Sutton

Paul D Breuder

Michael A Stapleton

Aimee D Wood

Jeff Van Tran

Muntaquim F Chowdhury

Matthew W Heath

Marcus W Song

Prashanth Nimmala

Mike Cornaby

Ray Ramadorai

Buderya S Acharya

Narayanan S Iyer

Jeff C Morris

Narayana S Iyer

James A Beavens

Xia Dia

Williard M Wiseman

Anat Deval

Brett W Newkirk

Dave Perchlik

Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Independent power control of processing cores

In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.

Launching a secure kernel in a multiprocessor system

In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.

Integrating intellectual property (IP) blocks into a processor

The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.

Dynamic voltage transitions

Methods and apparatus to improve integrated circuit (IC) performance across a range of operating conditions and/or physical constraints are described. In one embodiment, an operating parameter of one or more of processor cores may be adjusted in response to a change in the activity level of processor cores (e.g., the number of active processor cores) and/or a comparison of one or more operating conditions and one or more corresponding threshold values. Other embodiments are also described.

Integrated circuit performance improvement across a range of operating conditions and physical constraints

Growing community of inventors

Beaverton, WA, United States of America

Robert J Greiner