Hewlett-Packard Company

Robert J Gluss

Nicholas S Fiduccia

A method of integrating repeaters into an integrated circuit design model includes specifying a geometry of a plurality of separate cell blocks. These cell blocks are locations on a chip die supporting appropriate functional capabilities, such as arithmetic and logic functions, decoders, input/output, etc. A list identifying top level nets connecting the cell blocks is then generated and locations along these top level nets exceeding a maximum signal transmission criteria (e.g., RC interconnect constraints) are identified. Repeater constraint regions are defined apart from the cell blocks and include one or more of the locations identified. A list is then generated of top level nets to be repeated at respective repeater constraint regions. An HDL representation is generated of repeater blocks for placement within each of the repeater constraint regions. Wiring directives may then be automatically generated connecting the HDL representation of repeater blocks into the integrated circuit design model. The HDL representation is compatible with multiple levels of abstraction representing the integrated circuit design model including a presynthesis model of an integrated circuit written, for example, in RTL. The HDL representation may further be compatible with a behavioral model of the integrated circuit design model. Each of the repeater constraint regions is sized and located to facilitate integrating repeaters into the pre-placement design. The size and location of the repeater constraint regions may further provide that the maximum signal transmission criteria (e.g., RC interconnect constraints) are satisfied independent of a functional cell placement within each of the cell blocks such that driving, receiving, and repeater cells can all be placed anywhere within respective constraint regions without violation of the maximum signal transmission criteria.

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Robert J Gluss