International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Globalfoundries Singapore Pte. Ltd.

Elpis Technologies Inc.

Grund Technical Solutions

Robert J Gauthier, Jr

Souvick Mitra

JunJun Li

Christopher Stephen Putnam

Mujahid Muhammad

Kiran V Chatty

Tom C Lee

William R Tonti

John B Campi, Jr

Rahul Mishra

Jeffrey Scott Brown

Jed Hickory Rankin

Steven H Voldman

Michel J Abou-Khalil

Wagdi William Abadeer

James Paul Di Sarro

You Li

Alain F Loiseau

Shunhua Thomas Chang

Edward J Nowak

Robert Russell Robison

Yun Shi

Tsung-Che Tsai

Randy William Mann

Rajendran Krishnasamy

Mickey H Yu

Meng Miao

Andres Bryant

Anindya Nath

Mahmoud A Mousa

Junjun Li

Terence B Hook

Renata A Camillo-Castillo

Richard A Phelps

Nathan D Jack

Wei Liang

Toshiharu Furukawa

William F Clark, Jr

Minh H Tong

Andreas Daniel Stricker

Ephrem G Gebreselasie

Jack Allan Mandelman

David V Horak

Theodorus E Standaert

Charles W Koburger, Iii

John Atkinson Fifield

Dominic Joseph Schepis

Fariborz Assaderaghi

Ankit Srivastava

Peter Edwin Cottrell

Anupam Dutta

Stephen Scott Furkay

Erik Mattias Dahlstrom

Kyong Jin Hwang

Steven J Holmes

Vibhor Jain

Robert K Leidy

David Michael Fried

Eric Adler

Andreas Scholze

Xiaowei Tian

Faye D Baker

Edward W Sengle

Anthony K Stamper

Tenko Yamashita

Effendi Leobandung

Carl John Radens

John J Ellis-Monaghan

James William Adkisson

Chengwen Pei

Jeffrey Bowman Johnson

Huiming Bu

James Albert Slinkman

Albert Manhee Chu

Dale Warner Martin

Thomas A Wallner

Michael J Hauser

Steven M Shank

Shyue Seng Tan

Kirk David Peterson

Kerry Bernstein

Kai D Feng

Robert Mark Rassel

John Joseph Pekarik

Fen Chen

Xinshu Cai

Bradford Lawrence Hunter

Mahender Kumar

Carrie Ellen Cox

Andrew A Turner

John P Connor

Jie Zeng

Nathaniel Peachey

Alan L Roberts

Dustin Kenneth Slisher

Nathaniel R Chadwick

Jason E Cummings

John A Watson

Amol Anil Joshi

Ajay Raman

Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises a first well and a second well in the semiconductor substrate. The first and second wells have a first conductivity type. The structure further comprises a third well and a fourth well in the semiconductor substrate. The third and fourth wells have a second conductivity type, the third well includes a portion that overlaps with the first well, and the fourth well includes a portion that overlaps with the second well.

Electrostatic discharge protection devices

An integrated circuit (IC) structure with a conductive pathway through resistive semiconductor material, e.g., for bipolar transistors, is provided. The IC structure may include a resistive semiconductor material having a first end coupled to a first doped semiconductor material. The first doped semiconductor material has a first doping type. A doped well may be coupled to a second end of the resistive semiconductor material. The doped well has a second doping type opposite the first doping type. A second doped semiconductor material is coupled to the doped well and has the first doping type. The resistive semiconductor material is within a conductive pathway from the first doped semiconductor material to the second doped semiconductor material.

Integrated circuit structures with conductive pathway through resistive semiconductor material

Disclosed structures include a semiconductor controlled rectifier or bi-directional semiconductor controlled rectifier with a trigger voltage (Vtrig) that is tunable. Some structures include a semiconductor controlled rectifier with an Nwell and Pwell in a semiconductor layer, with a P-type diffusion region in the Nwell, and with an N-type diffusion region in the Pwell. Gate(s) on the well(s) are separated from the junction between the wells and from the diffusion regions. Other structures include a bidirectional semiconductor controlled rectifier with a Pwell between first and second Nwells in a semiconductor layer, with first P-type and N-type diffusion regions in the first Nwell, and with second P-type and N-type diffusion regions in the second Nwell. Gate(s) on the well(s) are separated from junctions between the Nwells and the Pwell and from any diffusion regions. In these structures, the gate(s) can be left floating or biased to tune Vtrig using gate leakage current.

Gate tunnel current-triggered semiconductor controlled rectifier

The present disclosure relates to semiconductor structures and, more particularly, to an electrostatic discharge device (ESD) with a pinch resistor and methods of manufacture. The structure includes: a semiconductor substrate; a shallow trench isolation structure extending into the semiconductor substrate; an amorphous layer in the semiconductor substrate and below the shallow trench isolation structure; and a pinch resistor between the shallow trench isolation structure and the amorphous layer.

Electrostatic discharge device with pinch resistor

Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.

Semiconductor device integration with an amorphous region

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a heterojunction bipolar transistor comprising a collector region, a base region and an emitter region; and at least one non-single-crystal semiconductor region in the collector region of the heterojunction bipolar transistor.

Heterojunction bipolar transistor with amorphous semiconductor regions

Embodiments of the disclosure provide an integrated circuit (IC) structure with resistive semiconductor material for a back well. The IC structure may include a semiconductor substrate having a deep well, and a device within a first portion of the deep well. The device includes a first doped semiconductor material coupled to a first contact, and a second doped semiconductor material coupled to a second contact. The deep well couples the first doped semiconductor material to the second doped semiconductor material. A first back well is within a second portion of the deep well. A first resistive semiconductor material is within the deep well and defines a boundary between the first portion of the deep well and the second portion of the deep well.

Integrated circuit structure with resistive semiconductor material for back well

The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region; an emitter region above the intrinsic base region; a collector region under the intrinsic base region; and an extrinsic base region comprising metal material, and which surrounds the intrinsic base region and the emitter region.

Bipolar transistors

The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure (ESD device) includes: a bipolar transistor comprising a collector region, an emitter region and a base region; and a lateral ballasting resistance comprising semiconductor material adjacent to the collector region.

Fin-based and bipolar electrostatic discharge devices

Embodiments of the disclosure provide an integrated circuit (IC) structure, including a triple well structure within a semiconductor substrate. A base region is within a doped well of the triple well structure, a collector terminal is within the doped well and laterally separated from the base region by a first insulator and a first avalanche junction is defined between a first pair of oppositely-doped semiconductor regions within the collector terminal. An emitter terminal is within the third doped well of the triple well structure and laterally separated from the collector terminal by a second insulator. A second avalanche junction is defined between a second pair of oppositely-doped semiconductor regions of the emitter terminal.

Integrated circuit structure with avalanche junction to doped semiconductor over semiconductor well

A structure includes trigger control circuitry for an SCR including: a first transistor having two P-type semiconductor terminals connected to an Nwell and a Pwell of the SCR; a second transistor having two N-type semiconductor terminals connected to the Pwell and ground; and, optionally, an additional transistor having two P-type semiconductor terminals connected to the Nwell and ground. Control terminals of the transistors receive the same control signal (e.g., RST from a power-on-reset). When a circuit connected to the SCR for ESD protection is powered on, ESD risk is limited so RST switches to high. Thus, the first transistor and optional additional transistor turn off and the second transistor turns on, reducing leakage. When the circuit is powered down, the ESD risk increases so RST switches to low. Thus, the first transistor and optional additional transistor turn on and the second transistor turns off, lowering the trigger voltage and current.

Operating voltage-triggered semiconductor controlled rectifier

The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a bipolar transistor device, including a base region, having a base contact region, in a first well of a first conductivity type, a collector region, having a collector contact region, in a second well of a second conductivity type, and an emitter region, having an emitter contact region, in the first well, located between the base contact region and the second well, and a reverse-doped resistance well, of the second conductivity type, located in the first well of the first conductivity type between the base contact region and the emitter contact region structured to decrease turn-on voltage of the bipolar transistor device.

Electrostatic discharge (ESD) device with improved turn-on voltage

The present disclosure relates to semiconductor structures and, more particularly, to improved turn-on voltage of high voltage electrostatic discharge device and methods of manufacture. The structure comprises a high voltage NPN with polysilicon material on an isolation structure located at a base region, the polysilicon material extending to at least one of a collector and emitter of a bipolar junction transistor (BJT), and the polysilicon material completely covering the base region of the BJT.

High voltage electrostatic devices

The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure comprising a vertical silicon controlled rectifier (SCR) connecting to an anode, and comprising a buried layer of a first dopant type in electrical contact with an underlying continuous layer of a second dopant type within a substrate.

High-voltage electrostatic discharge devices

Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P− closer to insulator layer). Additionally, to minimize parasitic capacitance, the gate structure may be shorter in length than contact regions parallel and adjacent thereto.

Semiconductor-controlled rectifier with low trigger voltage for electrostatic discharge protection

Growing community of inventors

Hinesburg, VT, United States of America

Robert J Gauthier, Jr