International Business Machines Corporation

Robert J Gauthier

William R Tonti

Toshiharu Furukawa

Robert Russell Robison

Souvick Mitra

JunJun Li

Wagdi William Abadeer

Kiran V Chatty

James Paul Di Sarro

Nathan D Jack

Jason E Cummings

Lilian Kamal, Legal Representative

Jed H Rankin, Jr

An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers

Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.

Forming an extremely thin semiconductor-on-insulator (ETSOI) layer

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Essex Junction, VA, United States of America

Robert J Gauthier