Globalfoundries Inc.

Globalfoundries U.S. Inc.

Robert J Fox, Iii

Roderick Alan Augur

Lili Cheng

Yusheng Bian

Luke G England

Sunil Kumar Singh

Jeannine Madelyn Trewhella

Nicholas A Polomoff

Kevin M Boyd

A photonic integrated circuit (PIC) die includes a silicon nitride optical component over an active region. Multiple interconnect layers are over the silicon nitride optical component, each of the multiple interconnect layers including a metal interconnect therein. At least one optical deflector is over the multiple interconnect layers and over the silicon nitride optical component. The optical deflector(s) may also include a contact passing therethrough to the interconnect layers, but do not include any other electrical interconnects. Each optical deflector may deflect light within an ambient light range of less than 570 nanometers (nm) to protect the silicon nitride optical component from light-induced degradation.

PIC die with optical deflector for ambient light

Methods of fabricating a structure for a metal-insulator-metal (MIM) capacitor. Conductive nanofibers are formed on a surface of a conductor layer. Each conductive nanofiber is terminated by an enlarged tip portion opposite the surface of the conductor layer. The enlarged tip portion is removed from each conductive nanofiber. The MIM capacitor may include the conductive nanofibers as portions of an electrode.

Metal-insulator-metal capacitors including nanofibers

Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. The MIM capacitor includes a layer stack with a first electrode, a second electrode, and a third electrode. The layer stack includes a pilot opening extending at least partially through at least one of the first electrode, the second electrode, and the third electrode. A dielectric layer is arranged over the metal-insulator-metal capacitor, and includes a via opening extending vertically to the pilot opening. A via is arranged in the via opening and the pilot opening. The pilot opening has a cross-sectional area that is less than a cross-sectional area of the via opening.

High-density metal-insulator-metal capacitors

Structures for interconnects and methods for forming interconnects. A dual-damascene opening is formed in a dielectric layer and a first liner is formed on the dielectric layer at one or more sidewalls of the dual-damascene opening. A first conductor layer is formed in a portion of the dual-damascene opening. The first liner is removed from the one or more sidewalls of the dual-damascene opening vertically between the first conductor layer and a top surface of the dielectric layer. After the first liner is removed, a second liner is formed on the dielectric layer at the one or more sidewalls of the dual-damascene opening between the first conductor layer and the top surface of the dielectric layer. A second conductor layer is formed in the dual-damascene opening between the first conductor layer and the top surface of the dielectric layer. The first and second liner materials differ in composition.

Interconnects with hybrid metallization

Interconnect structures and methods for forming an interconnect structure. A sacrificial layer is formed on a substrate and an interconnect opening is formed that extends vertically through the sacrificial layer into the substrate. The interconnect opening is filled with a conductor to form a conductive feature. After filling the interconnect opening with the conductor, a dielectric layer is formed on the sacrificial layer. After the dielectric layer is formed on the sacrificial layer, the sacrificial layer is removed to form an air gap layer arranged vertically between the dielectric layer and the substrate.

Integration of air gaps with back-end-of-line structures

A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a second crack stop pillar within an insulator region of the IC structure. The first crack stop pillar can include an overlapping via in contact with a top surface and at least one side surface of a first conductive element therebelow. The overlapping via of the first crack stop pillar may be in a given layer of the IC structure, and the second crack stop pillar may include a via in the given layer, the via extending to a different depth than the overlapping via. The via of the second crack stop pillar may be an overlapping via in contact with a top surface and at least one side surface of a second conductive element therebelow.

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Greenfield Center, NY, United States of America

Robert J Fox, Iii