International Business Machines Corporation

Robert J Finch

Richard James Evans

Gordon M Babson

Allen W Brouillette

Richard J Ross

Philip H Noel

George A May

A method of implementing electrostatic discharge (ESD) testing of an integrated circuit includes applying an ESD event to an exposed backside of a substrate of the integrated circuit, wherein the backside of the substrate is electrically isolated from circuit structures formed at a front-end-of-line (FEOL) region of the integrated circuit. The operation of the circuit structures is tested to determine whether the ESD event has caused damage to one or more of the circuit structures as a result of a breakdown in the electrical isolation between the circuit structures and the backside of the substrate.

Stress testing of silicon-on-insulator substrates using applied electrostatic discharge

A process and structure are disclosed for a programmable array for use in a read-only memory comprising diode elements and shorted diode elements. The elements are connected across bit and wordlines. The invention utilizes lateral polysilicon diodes and metal silicide layer bridging the junction of pre-selected diodes to short pre-selected diode elements. Programming is accomplished by either forming the silicide layer across the junctions of pre-selected diodes or removing the silicide layer from the junctions of pre-selected diodes.

ROM storage cell and method of fabrication

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Essex Junction, VT, United States of America

Robert J Finch