International Business Machines Corporation

Globalfoundries Inc.

Robert J Devins

David W Milton

Kenneth A Mahler

Robert Dov Herzl

Paul Mark Schanely

Pascal A Nsame

Peter Dean LaFauci

Mark E Kautzman

Patrick K Kam

Paul G Ferro

Paul J Ferro

Emory D Keller

Stephen Yik-fai Hon

Gordon Taylor Davis

Clarence Rosser Ogilvie

Robert Spencer Horton

Nagashyamala R Dhanwada

William E Mitchell

James R Robinson

James L Patrick, Jr

John Michael Krause

A method and system comprises transferring data from a first processor to at least one pulse generator directly connected to an interrupt control of at least a second processor. The transferring of the data bypasses memory. The method further includes reading the transferred data directly from the at least one pulse generator by the at least a second processor.

Method and system of communicating between peer processors in SoC environment

A development system for developing new peripheral software code for new peripheral hardware that will be used in a new integrated system. The development system includes a legacy, or preexisting, integrated system substantially the same as the new integrated system. A model of the new peripheral hardware is made. Each I/O register of the model is mapped into memory-mapped I/O space. Development code corresponding to the new peripheral software code is executed on the preexisting hardware so as to interact with the model via the memory-mapped I/O space. In one embodiment, the model is executed as an embedded model on the preexisting integrated system. In another embodiment, the model is executed as a non-embedded model on a hardware descriptive language simulator.

System and method for developing embedded software in-situ

Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.

Optimal bus operation performance in a logic simulation environment

A system and method for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.

Method of switching external models in an automated system-on-chip integrated circuit design verification system

A method and system comprises creating a test case that is dependent upon known sequences and executing the test case on an originating processor until it reaches a known point. The method further includes executing the test case on a different processor to perform an action and informing the originating processor that the action was taken. The action is verified as being occurred with the originating processor.

Method and system of coherent design verification of inter-cluster interactions

Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.

Method and system for logic verification using mirror interface

A method and system comprises extracting resources required to run a discrete test case or set of associated test cases on a design. The method and system further includes building a simulation model based on the extracted resources and executing the simulation model using only the extracted resources, exclusive of an entire design, to test a specific function or group of interrelated functions represented by the discrete test case or set of associated test cases for design verification, and correlating the simulation results with the test plan.

Method and system of design verification

A system for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.

A computer-implemented method and system for performing graphics rendering on demand on a graphics subsystem, with only nominal host system operations being required. High-level specifications of graphics operations in a computer program are captured as I/O hardware programs in a memory. A graphics processor in the subsystem issues instructions in the captured programs to a graphics accelerator, which executes the instructions to perform graphics operations. The graphics accelerator has a status indicator containing status information relating to hardware events incident to the graphics operations. Under the control of instructions in the captured program, the graphics processor monitors the status indicator, and either issues, or delays issuing, the instructions in the captured programs, depending upon the status information in the indicator.

Method and system for graphics rendering using hardware-event-triggered execution of captured graphics hardware instructions

A computer-implemented method and system for performing graphics rendering on demand on a graphics subsystem, with only nominal host system operations being required. An application program requiring graphics to be rendered is coded to bound a sequence of calls to basic rendering functions, defining a desired image to be rendered, between begin-program and end-program identifiers. When the application program is executed on a host operating system, a begin-program identifier invokes a function in a graphics device driver in the host system. The function captures the calls to the rendering functions within the application program in a memory as hardware instructions to the graphics subsystem. When the function encounters an end-program identifier, it registers the captured hardware instructions with the host system as an executable program. Subsequently, the application may render the image upon demand by calling the registered executable program, which will execute from the memory on the graphics subsystem, with only nomimal host processor operations being required. Thus, host processor operations and memory normally required for performing graphics rendering are conserved.

Method and system for graphics rendering using captured graphics hardware instructions

The time, effort and expense required to develop verification software for testing and de-bugging system-on-chip (SOC) designs represents a considerable investment. According to the method of the present invention, a portion of such verification software may be re-used in an operating system (OS) (i.e., a system used for, e.g., general business, technical or scientific applications as opposed to software testing) to capitalize on the investment. The verification software includes low-level device drivers (LLDDs) which were coded for and paired with specific device designs ('cores') throughout the verification process, and were consequently also verified (i.e., de-bugged) in the process. Thus, the low-level device drivers represent reliable software with detailed knowledge of the corresponding devices. By developing a thin middle-level device driver layer of software to interface between a particular OS and the lower-level device drivers, the LLDDs can be re-used in an OS that uses devices that the LLDDs were designed for. This frees SOC customers from having to develop low-level software and instead allows them to concentrate on developing their particular applications, or 'value-added' software.

Growing community of inventors

Essex Junction, VT, United States of America

Robert J Devins