Intel Corporation

Robert J Chroneos, Jr

Koushik Banerjee

Tom Mozdzen

Hamid Ekhlassi

Subramani Iyer

Ho Fang

The present disclosure is directed to an electrostatic charge measurement tool and dedicated system having a probe configured to scan the surface of a target, and methods for taking the electrostatic charge measurements. In an aspect, the probe is a non-contact electrostatic probe that may be moveable across the surface of the target and be adjustable in its height from the surface of the target. In another aspect, the target is an electrostatic chuck or semiconductor wafer. In a further aspect, the electrostatic charge measurement system may perform insitu measurement of targets without removing them from their working environment.

Electrostatic charge measurement tool

An electronic package which has a polygonal shaped heat slug. The heat slug extends from a top surface of a package which has a plurality of vias. The package also has a number of capacitors that are mounted to the top surface. Some of the capacitors are located between the heat slug and the vias. The polygonal shape of the heat slug provides additional space on the top surface so that capacitors can be added without eliminating vias from the package.

Method and apparatus for polygonal heat slug

An integrated circuit package. The package includes a substrate that has a first internal conductive bus and a second internal conductive bus that are located on a common layer of the substrate and dedicated to different power voltage levels. The busses are coupled to external lands located on a first surface of the package by vias that extend through the substrate. The first and second busses are located on a common layer of the substrate. The package contains an integrated circuit which is mounted to a heat slug that is attached to a second surface of the package. The integrated circuit is coupled to bond fingers located on a shelf of the substrate. Some of the bond fingers are connected to the internal busses by conductive strips that wrap around the edges of the shelf. Some of the vias are connected to a whole group of external lands. Grouping the lands to a single via reduces the number of vias on the second surface of the package. The reduction in vias allows additional capacitors to be mounted to the second surface of the package.

Integrated circuit package

A surface mountable pin connector has a substrate or a circuit board carrier, which has a number of through holes or vias formed therein, and a number of connector pins, each of which is soldered into a respective one of the through holes with high melt temperature solder. A damming device or protrusion is located on each pin nearer to the shoulder than typical interference fit protrusions. The damming device is sized and shaped to completely block the through hole or via.

Surface mount connector with pins in vias

Heat slug design which facilitates mounting of discrete components on a package without losing lands or pins in the package

Integrated circuit package which contains two in plane voltage busses

An integrated circuit package which contains an integrated circuit. The internal integrated circuit is coupled to external lands located on a first outer surface of the package by a plurality of vias. The vias extend through the package from the first outer surface to an opposite second outer surface. The package has a plurality of devices such as capacitors that are mounted to the second outer surface. Some of the vias are connected to a whole group of external lands. Grouping the lands to a single via reduces the number of vias on the second surface of the package. The reduction in vias allows additional capacitors to be mounted to the second surface of the package.

A method for plating an integrated circuit package. The method includes constructing a package which has a plurality of internal bond fingers that are subsequently coupled to an integrated circuit. The package contains a plurality of vias that are electrically connected to the bond fingers. The vias are also coupled to a layer of metallization that extends across an outer surface of the package. The meallization layer is used as a plating bar to plate the internal bond fingers. After plating the meallization layer is etched from the surface of the package.

Method for plating a bond finger of an intergrated circuit package

An integrated circuit package which has a plurality of bond fingers arranged in a staggered row arrangement on a bond shelf of the package. The bond shelf contains a first row of bond fingers that are separated by a plurality of spaces. The bond shelf also has a second row of bond fingers which each have a bond pad and a lead trace that extends through the spaces of the first row of bond fingers.

Growing community of inventors

Tempe, AZ, United States of America

Robert J Chroneos, Jr