Koninklijke Philips Corporation N.v.

Robert J Caesar, Jr

David R Evoy

Mark Bapst

D C Sessions

Timothy A Pontius

Mark Johnson

Arjan Bink

Ivan Svestka

In one example embodiment, data is transferred at high speeds over a parallel data bus without loss of data integrity by transferring the data encoded with the quantity of ones relatively the same as the quantity of zeroes. Consistent with one embodiment of the present invention, a bus-interface circuit encodes a set of X data bits into a set of Y data bits, where Y is greater than X. The encoding is implemented to approximately balance the number of ones and the number of zeroes in each set to be transmitted. A specific example application involves encoding the set of X data bits so that there is a balanced number of ones and zeroes in the set of Y data bits. In certain applications, the present invention is implemented to reduce current flow between transmitting and receiving modules and thereby reduce EMI, reduce the number of power pins required for the bus interface, and/or reduce the I/O delay and the skew from voltage sag in the signals passed over the parallel data bus.

Parallel communication based on balanced data-bit encoding

An embedded-controller-based system, such as a personal digital assistant (PDA), includes a system-on-a-chip with a processor, system bus, memory, and system-bus peripherals. The system-bus peripherals include connections to data paths that are not accessible from the system bus during execution of application programs. Associated with these connections are test drivers that include registers that can be written to by the processor via the system bus for software controllability. When the processor executes a test program, it writes test values to these registers. Some bits of the test values are used to control multiplexers so that they can decouple function block ports from the non-system-bus connections and then couple the remaining bits of the registers. In this way, a test program can write data directly to the non-system bus connections. The results of the test data being applied at the source of inter-block connections can be read from the destinations using test samplers. The test samplers can be taps to function block ports that are multiplexed to the system bus for reading during a test procedure for software observability. Thus, both bus connections and non-bus connections can be tested by a program running the system processor without requiring external test equipment.

Computer-system-on-a-chip with test-mode addressing of normally off-bus input/output ports

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Duluth, GA, United States of America

Robert J Caesar, Jr