Motorola Corporation

Robert J Burdge

Lansing M Carson

James William Startup

Leo B Conner

Stephen Chi Humg Ma

A multichannel time shared demodulator (10) is implemented in an efficient ASIC architecture that provides routing-of user voice channels and access channels to a collection of time-shared processors for rapid signal detection, tracking and demodulation. The channels are routed in a random order and then processed by a time-shared symbol synchronization processor (18) for voice channels and a time-shared detection processor for access channels. The signals are over-sampled via a time-shared interpolation filter. The interpolation process yields a ten to one over sampling ration of all signals. A synchronized clock is used to choose the phases of the interpolation filter outputs.

Multichannel time shared demodulator and method

A data communication receiver (10) uses a decision feedback demodulator (32) to remove data from a received signal. Quadrature components of the received signal define a received phase. The received phase is rotated (46) by an amount predicted to compensate for phase and frequency errors. After this rotation, a decision circuit (52) determines the modulation phase for a current symbol. A phase rotator (64) compares the modulation phase with the received phase to generate a measured phase error for the symbol. This measured phase error and measured phase errors from past symbols are averaged in a combination circuit (80) to produce a phase estimate. The past measured phase errors are also processed to determine the amount of change in measured phase error that has occurred over a number of symbols. This processing yields a frequency estimate. A phase rotator (94) merges the frequency and phase estimates for use in compensating a current received phase.

Decision feedback demodulator with phase and frequency estimation

A method for multiplexing a series of frequency division multiple access (FDMA) signals includes providing complex channels offset relative to the FDMA signals. Each FDMA signal is filtered to be centered and occupy one-half of the bandwidth of each complex channel, leaving an 'off' channel between each pair of successive FDMA signals. The real part of the multiplexed output signal is processed and higher frequency signals of FDMA signals image into the 'off' channels. Demultiplexing includes aligning a demultiplexing channelization pattern with the multiplexed input signal contained in input channels. The input channels are one-half a bandwidth of each of the complex channels. The input channels contain a sequence of FDMA signals separated by a reverse sequence of images of the FDMA signals. Consecutive even-numbered input channels correspond to consecutive complex channels of the complex channels and the sequence of FDMA signals can be extracted from the complex channels.

Method for FDMA signal multiplexing and demultiplexing

This circuit provides output detection pulses in response to interrogation signals for transponder systems which require a high degree of sensitivity and a low degree of false alarms. This circuit includes a tracking arrangement which monitors the level of noise and adjusts a control signal to exclude noise below a certain threshold. A comparator generates detection pulses in response to the input interrogation signals and the control signal. As a result, detection pulses are produced only for interrogation signals on a one-for-one basis. At the same time, the circuit adjusts its sensitivity so that low power interrogation signals (sufficiently above the noise level) may be accurately detected without responding excessively to noise. In addition, an active clamp circuit increases the gain and sensitivity of the circuit by clamping the noise level to approximately a ground state. The circuit is totally insensitive to the interrogation pulse amplitude and relatively insensitive to the interrogation pulse rate.

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Mesa, AZ, United States of America

Robert J Burdge