Hewlett-packard Company

Robert J Brooks

Michael L Ziegler

William R Bryg

James B Williams

Robert D Odineal

Thomas R Hotchkiss

John L Wood

Craig R Frink

Stephen G Burger

Brendan A Voge

K Monroe Bridges

Eric W Hamilton

Kenneth K Chan

Robert E Naas

Helen Nusbaum

A shared bus system having a bus and a set of client modules coupled to the bus. Each client module is capable of sending transactions on the bus to other client modules and receiving transactions on the bus from other client modules for processing. Each module has a queue for storing transactions received by the module for processing. A bus controller limits the types of transactions that can be sent on the bus to prevent any module's queue from overflowing.

Queue-based predictive flow control mechanism with indirect determination of queue fullness

Queue-based predictive flow control mechanism

A computing system includes a memory bus, an input/output bus, a main memory, and an input/output adapter. The memory bus provides information transfer. The input/output bus also provides information transfer. For example the input/output bus is an input/output bus onto which is connected input/output devices. The main memory is connected to the memory bus. The main memory includes a page directory. The page directory stores translations. Each translation in the page directory includes a portion of an address for data transferred over the input/output bus, for example, the page address portion of I/O bus address. Each translation in the page directory also is indexed by a portion of an address for a memory location within the main memory, for example, the page address portion of the address for the memory location. The input/output adapter is connected to the memory bus and the input/output bus. The input/output adapter includes an input/output translation look-aside buffer. The input/output translation look-aside buffer includes a portion of the translations stored in the page directory.

Translation mechanism for input/output addresses

A computing system is presented which includes a memory, an input/output adapter and a processor. The processor includes a write back cache in which dirty data may be stored. When performing a coherent write from the input/output adapter to the memory, a block of data is written from the input/output adapter to a memory location within the memory. The block of data contains less data than a full cache line in the write back cache. The write back cache is searched to determine whether the write back cache contains data for the memory location. When the search determines that the write back cache contains data for the memory location a full cache line which contains the data for the memory location is purged.

Partial cache line write transactions in a computing system with a write

A computing system includes a main memory and an input/output adapter. The input/output adapter accesses a translation map. The translation map maps input/output page numbers to memory address page numbers. Entries to the translation map are generated so that each entry includes an address of a data page in the main memory and transaction configuration information. The transaction configuration information is utilized by the input/output adapter during data transactions to and from the data page.

Access hints for input/output address translation mechanisms

A bus system having a bus arbitration scheme. The bus system includes a bus and a plurality of client modules coupled to the bus. Each of the client modules is capable of transmitting information on the bus to another of client module, and only one client module is entitled to transmit information on the bus at any time. A module entitled to transmit information on the bus has control of the bus for a minimum period of time defining a cycle. To determine which module is entitled to use the bus, each client module generates an arbitration signal when it seeks to transmit information on the bus. Each client module has an arbitration signal processor responsive to the arbitration signals for determining whether the module is entitled to transmit information on said bus. The system preferably also contains a host module that informs the client modules what types of transactions allowed on the bus in a given cycle. Each arbitration signal processor preferably is also responsive to the client option signals sent by the host module during an earlier cycle.

Fast pipelined distributed arbitration scheme

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Roseville, CA, United States of America

Robert J Brooks