Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Sync-n-scale, LLC

Robert J Blakely

John A Morrison

Christian Petersen

Ray Woodward

Robert B Smith

Karl Joseph Bois

Brandon Rubenstein

Eric M Rentschler

Samuel Martin Babb

Michael S Allison

Robert J Brooks

Bradley Dean Winick

Eugene Arthur Miksch

Leo J Embry

John S Atkinson

John R Feehrer

A method and system for authenticating computer nodes on a network, including providing a synchronized clock system, at a predetermined clock frequency, for use with an electronic system with a plurality of system nodes. Matching counters are connected to each of the plurality of system nodes, each of the counters being incremented in accordance with the clock frequency experienced by the system nodes to which the counters are connected. A difference is calculated between a count number at the end of a certain interval and the count number for the same counter at the beginning of the interval, to arrive at a count difference for each counter. The count difference of a particular counter is compared with the count difference of at least two other counters and, in the event that the count difference of the particular counter does not match, that node is noticed as an imposter.

Synchronous timestamp computer authentication system and method

An electronic device is disclosed herein. An embodiment of the electronic device comprises an electronic component, wherein the electronic component is operated by a DC voltage. The electronic component comprises an AC to DC converter that converts an AC voltage to the DC voltage, wherein the RMS value of the AC voltage is greater than the DC voltage. The electronic device further comprises a power supply comprising an input and an output. The input is connectable to a line voltage and the output is connected to the AC to DC converter of electronic component. The AC voltage is output by the output of the power supply.

Electronic device

A memory architecture includes at least one unbuffered dual inline memory module (DIMM). At least one advanced memory buffer (AMB) provides an interface between the at least one DIMM and a host memory controller.

Buffered memory architecture

System and methods of synchronizing reference frequencies are disclosed. In an exemplary implementation, a method may comprise providing separate reference frequencies for each of a plurality of operational components. The method may also comprise connecting the separate reference frequencies to one another in a modular, fault-tolerant circuit topology. The method may also comprise synchronizing the separate reference frequencies so that each of the operational components operate at the same frequency.

Systems and methods of synchronizing reference frequencies

A primary memory board is disclosed. The primary memory board comprises a printed circuit board (PCB) having a front side and a back side, a plurality of DIMM surface mount connectors, and at least one component. The plurality of DIMM surface mount connectors are mounted on the front side of the PCB. The at least one component is mounted on the back side of the PCB and is positioned opposite the location of at least one of the plurality of DIMM surface mount connectors mounted on the front side of the PCB.

Low profile DIMM board

Systems, methodologies, media, and other embodiments associated with connecting a cable to a computer component are described. One exemplary system embodiment includes a component connector comprising at least one signal pin and a plurality of ground pins positioned along a parameter of the at least one signal pin to surround the at least one signal pin. The example system may also include a receptacle connected to and in electrical contact with the plurality of ground pins. The receptacle can be configured with an opening to allow a cable connector to connect to the at least one signal pin.

Component connector

The present invention is directed to a method and apparatus for mitigating electromagnetic waves emanating from an electronic device. The apparatus comprises a cover member, a bight extending from one end of the cover member, and a retaining plate spaced from the cover member and connected to the bight to provide a biasing force away from the cover member and towards an electronic device. The cover member is configured to overlie an opening in the chassis of the electronic device and the retaining plate is configured to abut cabling extending out of the chassis. In this way, the apparatus attenuates electromagnetic waves radiating emanating from an opening in a chassis of an electronic device and conducted along cabling as a noise signal superimposed upon the intended signal.

Method and apparatus for mitigating electromagnetic waves

A capacitor mounting method and resulting printed circuit board that increases the mounting density of both vias and decoupling capacitors is presented. Vias are shared between capacitors mounted on the top and bottom of the printed circuit board. This arrangement allows increased decoupling capacitor density and avoids the current doubling problem when shared vias are connected with capacitors installed on the same side of the board.

Method for high-density, low-via-count, decoupling capacitor placement

An apparatus and a method are provided to distribute interrupts from a system bus to Intel&reg; Architecture (IA)-32 applications processors. The apparatus includes a bridge that couples a processor bus to the system bus. In addition, the bridge is coupled to an advanced programmable interrupt controller (APIC) by an APIC bus. The bridge monitors the system bus for interrupts and converts selected interrupt transactions into APIC messages. The bridge then sends the APIC messages to the APIC bus. Each of the applications processors is also coupled to one of many APIC buses. The applications processor that is the target of the interrupt transaction receives the APIC message and executes an interrupt handler routine. The apparatus and method also incorporate interrupt transaction buffering and throttling.

Apparatus and method for delivering interrupts via an APIC bus to IA-32 processors

An apparatus and method for permitting bus locking in a computer system having a mixed architecture. The mixed architecture includes a first bus coupled to processors that may run applications using bus locking or cache line locking. The apparatus interfaces the first bus with a second bus that does not support bus locking. The apparatus when presented with a locked transaction effectively implements bus locking on the second bus.

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Ft. Collins, CO, United States of America

Robert J Blakely