International Business Machines Corporation

Ibm Canada Limited - Ibm Canada Limitee

Robert J Blainey

James Lawrence McInnes

Roch Georges Archambault

Michael K Gschwind

Steven Jay Munroe

Yaoqing Gao

Cathy May

Hung Qui Le

Steven Wayne White

Bradly George Frey

Thomas James Heller, Jr

Mark Francis Wilding

Francis Patrick O'Connell

Charles Brian Hall

Christopher Michael Donawa

C Brian Hall

Susan Elizabeth Eisen

Kai-Ting Amy Wang

Barnaby Dalton

Allan Russell Martin

Alexander Abrashkevich

Harold W Cain

Michael R Meissner

Louis Ly

James A Sedgwick

Lior Velichover

Guy L Guthrie

Derek E Williams

Harold Wade Cain, Iii

Matthew Albert Huras

Raul Esteban Silvera

Ettore Tiotto

Randall Ray Heisch

Guansong Zhang

Arie Tal

Dmitri Abrashkevich

Pascal Vezolle

Daniel G Foisy

Taylor J Lloyd

John David McCalpin

Yogendra K Srivastava

Bradley G Frey

Sridhar Munireddy

Steven W White

Yingwei Zhang

Yaoging Gao

Brian C Hall

Heng Kuang

The present disclosure relates to minimizing the execution time of compute workloads in a distributed computing system. An example method generally includes receiving, from each of a plurality of server clusters, an estimated completion time and cost information predicted to be consumed in processing the compute workload. A workload manager compares the received estimates to a completion time and threshold cost criteria. Upon determining that the estimated completion time and cost information from any of the plurality of server clusters does not satisfy the completion time and threshold cost criteria, the workload manager partitions the compute workload into a plurality of segments, requests estimated completion time and cost information from the plurality of server clusters for each of the plurality of segments, and selects a cluster to process each segment of the compute workload based on the estimated completion time and cost reported for each segment.

Minimizing execution time of a compute workload based on adaptive complexity estimation

A computing system includes at least one processor and at least one module operable by the at least one processor to calculate a tail of a first dataset by determining elements of the first dataset that fall outside of a specified percentile, and determine locations of the first dataset at which elements of the first dataset that fall outside of the specified percentile are located. The at least one module may be operable to calculate a tail of a second dataset by populating a data structure with elements of the second dataset that correspond to the locations of the first dataset, and determining, using the data structure, elements of the second dataset that fall outside of the specified percentile. The at least one module may be operable to output an indication of at least one of the tail of the first dataset or the tail of the second dataset.

Efficient tail calculation to exploit data correlation

In a multiprocessor data processing system having a distributed shared memory system, a memory transaction that is a rewind-only transaction (ROT) and that includes one or more transactional memory access instructions and a transactional abort instruction is executed. In response to execution of the one or more transactional memory access instructions, one or more memory accesses to the distributed shared memory system indicated by the one or more transactional memory access instructions are performed. In response to execution of the transactional abort instruction, execution results of the one or more transaction memory access instructions are discarded and control is passed to a fail handler.

Rewind only transactions in a data processing system supporting transactional storage accesses

A method for recording and profiling information of a plurality of aborted transactions from a plurality of transactions is executed by processor core with a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.

Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memories

A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.

Recording and profiling transaction failure source addresses and states of  validity indicator corresponding to addresses of aborted transaction in hardware transactional memories

Embodiments of the present invention provide a method, system and computer program product for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management. In an embodiment of the invention, a method for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management can include setting different hardware registers with different priority values for correspondingly different transactions in a transactional memory system configured for transactional memory management according to respective priority values specified by priority assignment logic in external software support for the system. The method also can include detecting a conflict amongst the transactions in the system. Finally, the method can include applying conflict arbitration within the system based upon the priority values specified by the priority assignment logic in the external software support for the system.

Prioritization for conflict arbitration in transactional memory management

A method for executing a transaction in a data processing system initiates the transaction by a transactional-memory system coupled to that memory component. The method includes initiating the transaction by a transactional-memory system that is part of a memory component of the data processing system. The transaction includes instructions for comparing multiple parameters, and aborting the transaction by the transactional-memory system based upon a comparison of the multiple parameters.

Conditional transaction abort and precise abort handling

A method () or a diagnostic recording device () having transactional memory and a processor coupled to the transactional memory can store () contents of a transaction log () of the transactional memory, detect () an exception event, and replay () last instructions that led up to the exception event using a debugger tool (). The transactional memory can be hardware or software based transactional memory. The processor can also store the transaction log by storing the contents of the transaction log in a core file () which can include a stack (), a register dump (), a memory dump (), and the transactional log. The debugger tool can be used to load up the core file, an executable file (), and a library () to enable the diagnostic recording device to retrace transactions occurring at the diagnostic recording device up to the exception event.

Method and apparatus for diagnostic recording using transactional memory

Generating decode time instruction optimization (DTIO) object code that enables a DTIO enabled processor to optimize execution of DTIO instructions. A code sequence configured to facilitate DTIO in a DTIO enabled processor is identified by a computer. The code sequence includes an internal representation (IR) of a first instruction and an IR of a second instruction. The second instruction is dependent on the first instruction. A schedule associated with at least one of the IR of the first instruction and the IR of the second instruction is modified. The modifying includes generating a modified schedule that is configured to place the first instruction next to the second instruction. An object file is generated based on the modified schedule. The object file includes the first instruction placed next to the second instruction. The object file is emitted.

Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization

A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted.

Compiling code for an enhanced application binary interface (ABI) including identifying, by a computer, a code sequence configured to perform a variable address reference table function including an access to a variable at an offset outside of a location in a variable address reference table. The code sequence includes an internal representation (IR) of a first instruction and an IR of a second instruction. The second instruction is dependent on the first instruction. A scheduler cost function associated with at least one of the IR of the first instruction and the IR of the second instruction is modified. The modifying includes generating a modified scheduler cost function that is configured to place the first instruction next to the second instruction. An object file is generated responsive to the modified scheduler cost function. The object file includes the first instruction placed next to the second instruction. The object file is emitted.

Linking code for an enhanced application binary interface (ABI) with decode time instruction optimization

A mechanism for minimizing effective memory latency without unnecessary cost through fine-grained software-directed data prefetching using integrated high-level and low-level code analysis and optimizations is provided. The mechanism identifies and classifies streams, identifies data that is most likely to incur a cache miss, exploits effective hardware prefetching to determine the proper number of streams to be prefetched, exploits effective data prefetching on different types of streams in order to eliminate redundant prefetching and avoid cache pollution, and uses high-level transformations with integrated lower level cost analysis in the instruction scheduler to schedule prefetch instructions effectively.

Fine-grained software-directed data prefetching using integrated high-level and low-level code analysis optimizations

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Newmarket, Canada

Robert J Blainey