Bull Hn Information Systems, Inc.

Robert J Baryla

William A Shelly

Minoru Inoshita

Charles P Ryan

Wayne R Buzby

Lowell D McCulley

Elisabeth Vanhove

In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by a given processor by performing successive swap operations between the memory and the given processor's shared cache, and the given processor's shared cache and private cache. If the gateword is found to be OPEN, it is CLOSEd by the given processor, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword CLOSEd in memory such that the given processor obtains exclusive access to the governed common code/data. When the given processor completes use of the common code/data, it writes the gateword OPEN in its private cache, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword OPEN in memory.

Equal access to prevent gateword dominance in a multiprocessor write-into-cache environment

A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller including pairs of half-block operand buffers, each divided into quarter block segments. The operand buffer set is coupled to selectively receive, under control of an input multiplexer, requested information blocks from the CPU bus in quarter-block segments and is further coupled to selectively send, under control of an output multiplexer, received quarter-block segments to the CPU and received full blocks to the cache memory.

Information block transfer management in a multiprocessor computer

A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for storing identification words identifying information blocks resident in the cache memory and including a status field indicative of the write permission authority the local CPU has on the block, an output buffer for storing the identification words of a block resident in the cache memory for which the CPU does not have and seeks write permission and for selectively sending identification words and an invalidate command onto the CPU bus, an input buffer for storing the identification words of all recent write permission requests in the group, a comparator for comparing the identification words in the output buffer with the identifications in the input buffer and control logic, responsive to the comparator sensing a compare condition (typically indicating a request by another CPU for write permission on the same block for which the local CPU has also requested write permission), for aborting the write permission request of the local CPU and establishing a retry process.

Multiprocessor computer system incorporating method and apparatus for

A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for identifying information blocks resident in the cache memory, logic for identifying cache misses on requests from the CPU, a cache miss output buffer for storing the identifications of a missed block and a block to be moved out of cache memory to make room for the requested block and for selectively sending the identifications onto the CPU bus, a cache miss input buffer stack for storing the identifications of all recently missed blocks and blocks to be swapped from all the CPUs in the group, a comparator for comparing the identifications in the cache miss output buffer stack with the identifications in the cache miss input buffer stack and control logic, responsive to the first comparator sensing a compare (indicating a request by another CPU for the block being swapped), for inhibiting the broadcast of the swap requirement onto the CPU bus and converting the swap operation to a 'siphon' operation to service the request of the other CPU.

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Phoenix, AZ, United States of America

Robert J Baryla