Anokiwave, Inc.

M/a -com, Inc.

Autoliv Asp, Incorporated

Tyco Electronics Corporation

Veoneer Us, Inc.

Robert Ian Gresham

Robert J McMorrow

David W Corman

Nitin Jain

Vipul Jain

Kristian N Madsen

Gaurav Menon

Jonathan P Comeau

Wade C Allen

Alan Peter Jenkins

Shmuel Ravid

Scott R Humphreys

Robert Gyorgy Egri

Andrew Michael Street

Yumin Lu

M Tekamul Buber

Adil Khalil

Robert Warren Point

Ryosuke Ito

Tissana T Kijsanayotin

Ratana Wohlert

Register banks are used to allow for fast beam switching in a phased array system. Each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Phased array control circuit for controlling directivity of a beam-formed signal

A conditioning integrated circuit (CDIC) chip can be used to aggregate signals to/from a number of beam forming integrated circuit (BFIC) chips, and signals to/from a number of CDIC chips can be aggregated by an interface integrated circuit (IFIC) chip. The CDIC chip includes temperature compensation circuitry to adjust the gain of the transmit and receive signals as a function of temperature based on inputs from a temperature sensor. The CDIC may include a plurality of beam forming channels each having a transmit circuit and a receive circuit, a common port coupled to the beam forming channels for selectively providing a common transmit signal to the beam forming channels and receiving a common receive signal from the beam forming channels, and a temperature compensation circuit configured to provide variable attenuation to the common transmit signal and the common receive signal based on a temperature sense signal.

Phased array architecture with distributed temperature compensation and integrated up/down conversion

A phased array system has a plurality of beam-forming elements, and a plurality of beam-forming integrated circuits in communication with the beam-forming elements. Each beam-forming integrated circuit has a corresponding register bank with a plurality of addressable and programmable register sets. In addition, each beam-forming integrated circuit has at least two different types of beam-forming ports. Specifically, each beam-forming element has a serial data port for receiving serial messages, and a parallel mode data port for receiving broadcast messages. Both the serial and broadcast messages manage the data in its register bank. The beam-forming integrated circuits receive the broadcast messages in parallel with the other beam-forming integrated circuits, while the beam-forming integrated circuits receive the serial messages serially&#x2014;sequentially with regard to other beam-forming integrated circuits.

Phased array with low-latency control interface

In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Phased array control circuit for controlling the effective shape of a beam-formed signal

Exemplary embodiments dynamically select the LO frequency and mixer mode (i.e., low-side LO injection or high-side LO injection) for upconversion based on the desired RF output frequency in order to mitigate the effects of spurious and LO leakage signals that could violate radiation emission limits, e.g., in the case where the IF signal frequency is smaller than the RF operating band. By dynamically switching the LO frequency and mixer mode as a function of the requested operating RF channel, low-level emissions and spurious signal compliance with restricted bands can be achieved.

Spur mitigation in a heterodyne upconversion system

In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be preprogrammed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Phased array control circuit

A beamforming integrated circuit has a single channel with a transmit chain and a receive chain. The transmit chain is configured to transmit an output signal and, in a corresponding manner, the receive chain is configured to receive an input signal. The integrated circuit also has separate horizontal and vertical polarity ports, and a double pole, double throw switch operably coupled between the chains and the ports. The double pole, double throw switch is configured to switch between operation in a first mode and a second mode.

Phased array with beamforming integrated circuit having two signal chains

A system and a method for calibrating an output signal of an antenna is disclosed. In one aspect, an apparatus includes a first digital adder configured to generate a gain offset by at least adding gain calibration data from non-volatile memory and gain command data from static memory. The apparatus further includes an amplitude gain circuit configured to modify, based at least in part on the gain offset, an amplitude of a first output signal of a first antenna. The modified amplitude of the first output signal is provided to enable pre-calibration of the first output signal. The apparatus further includes a power detector configured to measure an output power of the first output signal. The apparatus further includes at least one processor configured to generate a difference between the measured and expected output power, and adjust gain command data in response to the generated difference.

Power detector calibration in integrated circuits

A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and first and second sets of integrated circuits on the laminar substrate. The first set of integrated circuits, each of which are single polarity integrated circuits, connects with a first set of the plurality of elements, and are configured to operate using first signals having a first polarity. In a similar manner, each one of the second set of integrated circuits also is a single polarity integrated circuit and connects with a second set of the plurality of elements. Also, each of the second set of integrated circuits is configured to operate using second signals having a second polarity. The first polarity is substantially orthogonal to the second polarity (i.e., to not interfere with each other).

Dual phased array with single polarity beam steering integrated circuits

In some example implementations, there may be provided methods for beamforming calibration of active electronically steered arrays (AESA). In some implementations, one or more adders may generate a phase offset by adding phase calibration data from non-volatile memory and phase command data from static memory, and/or generate a gain offset by adding gain calibration data from the non-volatile memory and gain command data from the static memory. Further, a phase-shift circuit can modify, based on the phase offset, a phase of a first output signal, and an amplitude gain circuit can modify, based on the gain offset, an amplitude of the first output signal. In accordance with these implementations, the modified phase of the first output signal and the modified amplitude of the first output signal are provided to enable pre-calibration of the first output signal and/or a first antenna. Related systems, methods, and articles of manufacture are also described.

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Somerville, MA, United States of America

Robert Ian Gresham