Xilinx, Inc.

Robert I Fu

Brian C Gaide

Chi Minh Nguyen

Steven P Young

Michael J Hart

James M Simkins

Santosh Yachareni

Ilya K Ganusov

Philip D Costello

Shidong Zhou

Praful Jain

Pierre Maillard

Anil Kumar Kandala

Sandeep Vundavalli

Vikram Santurkar

Brian D Philoksky

The disclosed circuit arrangements include a logic circuit, input register logic coupled to the logic circuit and including a first plurality of bi-stable circuits and a control circuit coupled to the input register logic. The control circuit is configured to generate a plurality of delayed clock signals from an input clock signal. The plurality of delayed clock signals include a first delayed clock signal and a second delayed clock signal. The control circuit selectively provides one or more of the delayed clock signals or the input clock signal to clock inputs of the first plurality of bi-stable circuits and selectively provides one or more of the delayed clock signals or the input clock signal to the logic circuit. The control circuit includes a variable clock delay logic circuit configured to equalize a clock delay to the input register logic with a clock delay to the logic circuit.

Selectively providing clock signals using a programmable control circuit

The disclosed voting circuit includes a pull-up circuit connected to an output node and to a positive supply voltage. A pull-down circuit is connected to the output node and to ground, and the output node is coupled to receive true output of a first bi-stable circuit. The pull-up circuit pulls the output node to the positive supply voltage in response to complementary output signals from second and third bi-stable circuits being in a first state, and the pull-down circuit pulls the output node to ground in response to complementary output signals from second and third bi-stable circuits being in a second state that is opposite the first state.

Voting circuit and self-correcting latches

A circuit for preventing multi-bit upsets induced by single event transients is described. The circuit comprises a clock generator configured to generate a first clock signal and a second clock signal; a first memory element configured to receive a first input signal and generate a first output signal, the first memory element having a first clock input configured to receive the first clock signal; and a second memory element configured to receive the first output signal and generate a second output signal, the second memory element having a second clock input configured to receive the second clock signal; wherein the first clock signal is the same as the second clock signal. A method of preventing multi-bit upsets induced by single event transients is also described.

Circuit for and method of preventing multi-bit upsets induced by single event transients

An interconnect multiplexer comprises a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer; an output inverter coupled to the outputs of the plurality of CMOS pass gates, wherein an output of the output inverter is an output of the interconnect multiplexer; and a plurality of memory elements coupled to the plurality of CMOS pass gates; wherein inputs to the plurality of CMOS pass gates are pulled to a common potential during a startup mode. A method of reducing contention currents in an integrated circuit is also disclosed.

Interconnect multiplexers and methods of reducing contention currents in an interconnect multiplexer

Integrated circuits having groups of flip-flops with the option to ignore control signals are disclosed. For example, an integrated circuit comprises a first group and a second group of flip-flops that share a common reset signal, and a first selection unit for selecting a first output from among the common reset signal and a logical low signal to be sent to the second group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the second group. The integrated circuit may also include a second selection unit for selecting a second output from among the common reset signal and a logical low signal to be sent to the first group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the first group.

Flip-flop array with option to ignore control signals

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Saratoga, CA, United States of America

Robert I Fu