Texas Instruments Corporation

Robert Henry Bell

Paul T Bennett

Sang Yong Lee

Steven L Harris

Robert Kenneth Oppen

Jiandong Jiang

W David Pace

DC to DC converters and PWM controllers are presented in which a slope compensation ramp signal is provided for current control operation via a frequency adaptive compensation circuit with a phase locked loop that provides a control output signal having an amplitude generally proportional to the frequency of a clock signal, and a slope generator circuit generating the slope compensation ramp signal with an amplitude generally proportional to the control output signal amplitude.

DC to DC converter and PWM controller with adaptive compensation circuit

A method includes generating a drive signal for a transistor in a switching regulator. The drive signal turns the transistor on and off to generate a regulated output voltage. The drive signal is generated based on a clock signal. The method also includes dynamically decreasing a frequency of the clock signal to decrease a dropout voltage of the switching regulator. Dynamically decreasing the frequency of the clock signal can increase a duration of switching periods defined by the clock signal. The dropout voltage could have a first value proportional to T/Tduring shorter switching periods and a second value proportional to T/Tduring longer switching periods. Trepresents a minimum amount of off-time for the transistor during each switching period, Trepresents a maximum amount of on-time for the transistor during shorter switching periods, and Trepresent a maximum amount of on-time for the transistor during longer switching periods.

Buck regulators with adjustable clock frequency to achieve dropout voltage reduction

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Prescott, AZ, United States of America

Robert Henry Bell