International Business Machines Corporation

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The Carborundum Company

Robert Hannon

Mukta G Farooq

Subramanian Srikanteswara Iyer

Sampath Purushothaman

Roy Rongqing Yu

Benjamin V Fasano

Steven John Koester

Subhash Laxman Shinde

Lester W Herron

David B Goland

Gregory M Johnson

Andrew Michael Reitter

Carla Natalia Cordero

Fei Liu

Richard Paul Volant

Emily R Kinser

Albert M Young

Herbert Lei Ho

Jon Alfred Casey

Niranjan Mohanlal Patel

Rao Venkateswara Vallabhaneni

Jonathan H Harris

Richard A Bates

Lisa M Studzinski

Robert A Youngman

Laertis Economikos

Ian D Melville

Kevin R Winstel

Richard Philip Surprenant

Paul Stephen Andry

Kevin Shawn Petrarca

Thomas M Shaw

Xiao Hu Liu

Ravi Mahendra Todi

Michael Wayne Lane

Troy Lawrence Graves-Abe

Liang-Kai Han

Ian D W Melville

Dae-Young Jung

Kangguo Cheng

Daniel C Edelstein

Geng Wang

Chandrasekharan Kothandaraman

Babar Ali Khan

Brian Joseph Greene

Bomy A Chen

Roger Allen Booth, Jr

Stuart A Sieg

Cornelia K Tsang

William Francis Landers

Gerd Pfeiffer

Scott R Stiffler

Scott W Crowder

Hsing-Jen C Wann

Mukesh Vijay Khare

Charles J Hendricks

Christopher N Collins

S Sundar Kumar Iyer

Jay G Harrington

Thomas J VanDuynhoven

Mukta G Rarooq

Comelia K Tsang

Da-Young Jung

S Sundar K Iyer

S Sundar Iyer

Sampath Porushothaman

A method of making a semiconductor device includes disposing a mask on a substrate; etching the mask to form an opening in the mask; etching a trench in the substrate beneath the opening in the mask; and implanting a dopant in an area of the substrate beneath the opening of the mask, the dopant capable of gettering mobile ions that can contaminate the substrate; wherein the dopant extends through the substrate from a sidewall of the trench and an endwall of the trench.

Implant after through-silicon via (TSV) etch to getter mobile ions

A method of implementing three-dimensional (3D) integration of multiple integrated circuit (IC) devices includes forming a first insulating layer over a first IC device; forming a second insulating layer over a second IC device; forming a 3D, bonded IC device by aligning and bonding the first insulating layer to the second insulating layer so as to define a bonding interface therebetween, defining a first set of vias within the 3D bonded IC device, the first set of vias landing on conductive pads located within the first IC device, and defining a second set of vias within the 3D bonded IC device, the second set of vias landing on conductive pads located within the second device, such that the second set of vias passes through the bonding interface; and filling the first and second sets of vias with a conductive material.

Three dimensional integrated circuit integration using dielectric bonding first and through via formation last

A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.

Computer readable medium encoded with a program for fabricating 3D integrated circuit device using interface wafer as permanent carrier

A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor is formed in the deep trench. The through-silicon-via connects the deep trench capacitor to the devices.

Method and structure for forming a deep trench capacitor

A method for printing a wafer ID on a wafer, the method comprises identifying a wafer ID on a back side of the wafer. Subsequently, etching a plurality of recesses, consistent in size with chip features of the wafer, into the front side of the wafer, such that the plurality of recesses depicts the wafer ID. The method further comprises filling the recesses with a metal.

Front side wafer ID processing

A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P&#x2212; layer, and the P&#x2212; layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P&#x2212; layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P&#x2212; layer. Also provided are a non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

3D integrated circuit device fabrication with precisely controllable substrate removal

A through-substrate via (TSV) structure that is immune to metal contamination due to a backside planarization process is provided. After forming a through-substrate via (TSV) trench, a diffusion barrier liner is conformally deposited on the sidewalls of the TSV trench. A dielectric liner is formed by depositing a dielectric material on vertical portions of the diffusion barrier liner. A metallic conductive via structure is formed by subsequently filling the TSV trench. Horizontal portions of the diffusion barrier liner are removed. The diffusion barrier liner protects the semiconductor material of the substrate during the backside planarization by blocking residual metallic material originating from the metallic conductive via structure from entering into the semiconductor material of the substrate, thereby protecting the semiconductor devices within the substrate from metallic contamination.

Metal-contamination-free through-substrate via structure

Method for fabricating 3D integrated circuit device using interface wafer as permanent carrier

The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

Optimized annular copper TSV

A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P&#x2212; layer, and the P&#x2212; layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P&#x2212; layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P&#x2212; layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.

Alignment marks to enable 3D integration

A 3D integrated circuit structure is provided. The 3D integrated circuit structure includes an interface wafer including a first wiring layer, a first active circuitry layer including active circuitry, and a wafer including active circuitry. The first active circuitry layer is bonded face down to the interface wafer, and the wafer is bonded face down to the first active circuitry layer. The first active circuitry layer is lower-cost than the wafer.

3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer

A process of forming three-dimensional (3D) die. A plurality of wafers are tested for die that pass (good die) or fail (bad die) predetermined test criteria. Two tested wafers are placed in proximity to each other. The wafers are aligned in such a manner so as to maximize the number of good die aligned between the two wafers. The two wafers are then bonded together and diced into individual stacks of bonded good die.

3D multiple die stacking

Growing community of inventors

Wappingers Falls, NY, United States of America

Robert Hannon