Hughes Aircraft Company

Hrl Laboratories, LLC

Robert H Walden

Adele E Schmitz

Gabor C Temes

Mark Lui

Tanju Cataltepe

Mark K Yu

Daniel Yap

William M Clark, Jr

Lawrence E Larson

Joseph F Jensen

Mark W Utlaut

A photonically sampled analog-to-digital converter using parallel channels of sampling and quantizing. The parallel combination achieves cancellation of the spurs that result from the nonlinear transfer function of the samplers. The samplers feed a dual-detector optoelectronic receiver that has differential inputs for suppression of laser intensity noise. The outputs of the multiple photonic samplers are averaged to reduce the effects of shot or thermal noise from the optoelectronic receiver of a sampler. The errors produced by the quantization process can be reduced by using a delta-sigma modulator-based analog-to-digital convertor as the quantizer which provides noise-spectrum shaping and filtering.

Photonic parallel analog-to-digital converter

A Schottky diode, and a method of making the same, which is fabricated on InP material and employs a Schottky layer including In Al As with x>0.6, or else including a chirped graded supperlattice in which successive periods of the superlattice contain progressively less GaInAs and progressively more AlInAs, the increase in AlInAs being terminated before the proportion of AlInAs within the last period (adjacent the anode metal) exceeds 80%. Such fabrication creates an InP-based Schottky diode having a low turn-on voltage which may be predictably set within a range by adjusting the fabrication parameters.

Low turn-on voltage InP Schottky device and method

A Schottky diode, and a method of making the same, which is fabricated on InP material and employs a Schottky layer including In,Al,AS with x>0.6, or else including a chirped graded superlattice in which successive periods of the superlattice contain progressively less GaInAs and progressively more AlInAs, the increase in AlInAs being terminated before the proportion of AlInAs within the last period (adjacent the anode metal) exceeds 80%. Such fabrication creates an InP-based Schottky diode having a low turn-on voltage which may be predictably set within a range by adjusting the fabrication parameters

Low turn-on voltage indium phosphide Schottky device and method

Focussed ion beam (FIB) implants (38,40) are used to set the threshold voltages of metal-oxide-semiconductor field-effect transistors (MOSFETs) in a selected logic gate (34,36) in a microelectronic integrated digital logic circuit (31) such that the direct current (DC) transfer function and logic thresholds are essentially the same as for another logic gate (30,32) which is not altered by FIB implants, but the switching speed is greatly reduced. This causes the altered gate (34,36) to switch in an apparently normal manner when tested under DC or low speed conditions, but to not switch at normal operating speed. The altered or disguised gate (34,36) is thereby always on or always off at the normal operating speed, whereas the unaltered gate (30,32) switches in the normal manner. This impedes attempts at reverse engineering since the circuit (31) operates differently under test and operating conditions, and the true logic functions of the gate (34,36) cannot be determined by known low speed test procedures.

Method for disguising a microelectronic integrated digital logic

Dynamic circuit disguise for microelectronic integrated digital logic

A precision sigma-delta analog-to-digital converter disposed to operate at a sampling rate giving rise to a relatively low oversampling ratio is disclosed herein. The high-order sigma-delta analog-to-digital converter (10) of the present invention is operative to convert an analog input signal to a digital output sequence. The inventive converter (10) includes a first integrating network (14) for generating a first sampled analog signal (X.sub.1) in response to the analog input signal. A second integrating network (18) generates a second sampled analog signal (X.sub.2) in response to the first sampled analog signal (X.sub.1). A third integrating network (22) generates a third sampled analog signal (X.sub.3) in response to the second sampled analog signal (X.sub.2). The sigma-delta converter (10) of the present invention further includes an internal quantizer (24) for generating the digital output sequence in response to the third sampled analog signal. A feedback network (28, 30) supplies the first, second and integrating networks (14, 18 and 22) with an analog feedback signal generated in response to the digital output sequence.

High-order sigma-delta analog-to-digital converter

A precision sigma-delta A/D converter having a desired number of cascaded stages is disclosed herein. The multi-stage sigma-delta analog-to-digital converter (10) of the present invention is operative to convert an analog input signal X(z) to an output sequence of digital words. The converter (10) of the present invention includes a first sigma-delta converter stage (14) for generating a first sequence of digital words and a quantization error signal in response to the analog input signal X(z). An interstage amplifier (34) then amplifies the quantization error signal by a first gain factor G. The present invention further includes a second sigma-delta converter stage (18) for generating a second sequence of digital words in response to the amplified quantization error signal. The first and second sequences are next filtered by a digital noise cancellation network (31, 32) and the filtered second sequence is divided by the first gain factor G via a divider circuit (38). A summing circuit (40) provides the output sequence of digital words by summing the filtered first sequence and the divided second sequence. The digital noise cancellation network (32) is also used to compensate for errors due to analog component imperfections, e.g., capacitor mismatches and finite operational amplifier gain.

Multi-stage sigma-delta analog-to-digital converter

A charge-coupled device (CCD) is provided with a dopant implant gradient, lateral channel stops and blocking implants by means of a focused ion beam (FIB). The FIB is repeatedly scanned across each cell of the CCD as a succession of overlapping but discrete implant scans. The doping levels of the FIB implants accumulate to a stepwise approximation of a desired dopant density profile, the widths of the steps being no greater than about half the widths of the discrete FIB implants. With a FIB pixel of about 750-1,500 Angstroms, the widths of the steps are preferably about 250-500 Angstroms; the dimension of the cells in the dopant gradient direction can be made less than about 5 microns. The lateral channel stops and back blocking implants can be as narrow as single FIB pixel widths, thus freeing up more of the cell for charge carrying capacity.

Charge-coupled device with focused ion beam fabrication

An analog-to-digital converter 10 employs a series of comparators 12, 14, 16 and 18. Each comparator includes at least one inverter consisting of a CMOS transistor pair including a P-channel transistor 22 and N-channel transistor 24. The threshold levels of the transistors 22, 24 are modified using focused ion beam implantation techniques to provide the comparators with monotonically increasing transistion levels.

Growing community of inventors

Newbury Park, CA, United States of America

Robert H Walden