Lucent Technologies Inc.

At+t Corp.

Robert H Vaiden

Dewayne Alan Spires

John C Gammel

Douglas G Marsh

Edward J Zimany, Jr

Ronald Joseph Rees

Benjamin H Evert

Christine Mary Gervesh

Randy Lee Hafer

Automatic testing a group of line circuits on a smart line card served by a central switch over a PCM bus is localized by using the microprocessor/DSP that provides codec functions for the group of line circuits. Tests such as DC overhead that are not performable by the central switch over the PCM bus are performed by the microprocessor/DSP when informed by the central switch that at least one of the channels is not processing voice signals. The microprocessor/DSP controls test switches on the line card to set-up various test terminations for the idle circuit as well as to selectively control the gain of the idle channel's amplifiers. The microprocessor/DSP synthesizes test tones and executes test tone detection processes within the time slot intervals accorded by the central switch to the idle channel. Among the tests performed are Forward Loop Gain with different resistance terminations, cable and fuse tests, DC overhead, and idle channel noise utilizing a limited number of test routines such as tone generation, DC generation, discrete Fourier transform, peak detection and variance from acceptable limits. The pass/fail condition of the idle channel under test is reported to the central switch.

Self-testing of smart line cards

A method and structure for automatically calibrating various paths within multi-channel analog integrated circuits is disclose. The invention calls for digital signal processing circuitry to correct for absolute gain differences in the multiple channels. A first reference channel is precision trimmed at manufacture and used by the digital processing circuitry as a reference for channel gain calibration. When the circuit is powered for use, the other channels are calibrated based on the trimmed and calibrated reference. The need for providing the circuitry to precision trim all other channels but one is avoided by this invention.

Reducing the number of trim links needed on multi-channel analog

CODECs and various other types of communication devices require timing information to enable them to transmit and receive digital information at the proper time. In the case of multiple CODECs on a single integrated circuit, this has typically required devoting terminals to provide separate transmit and receive frame synchronization pulses for each CODEC. Alternatively, a microprocessor interface may be included so that internal registers can be loaded with transmit and receive timing information. However, that approach limits timing flexibility. In the present invention, a 'frame synchronization separation pulse' (FSEP) provides the separation in time between transmit and receive synchronization pulses. In this manner, the number of integrated circuit terminals required for synchronization may be reduced.

Synchronization of multiple transmit/receive devices

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Allentown, PA, United States of America

Robert H Vaiden