Lattice Semiconductor Corporation

Advanced Micro Devices Corporation

Robert H Tu

Sunil D Mehta

Xiao-yu Li

Chun Jiang

Ting Yiu Tsui

Christopher O Schmidt

An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. A P&plus; implant is provided at the tunnel window edge. During the programming operation, the P&plus; contacted inversion layer is used instead of the program junction. As a result, there is eliminated the voltage drop in the program junction region so as to improve the efficiency of programming.

EEPROM tunnel window for program injection via P&plus; contacted inversion

A non-volatile memory cell is disclosed with increased drive current. A low voltage read transistor is used to increase the drive current. However, with a low voltage read transistor, extra protection is needed to ensure the read transistor is not damaged by high voltage. In one aspect, an isolation transistor is inserted between the read transistor and a sense transistor. The isolation transistor, read transistor and sense transistor are connected in series. When a high voltage is used during an erase operation of the memory cell, the isolation transistor absorbs some of the voltage to protect the read transistor from an excessive voltage level.

Non-volatile memory cell with enhanced cell drive current

Eeprom tunnel window for program injection via P&plus; contacted inversion

A method of manufacturing a semiconductor device with reduced shallow trench isolation defects and stress is disclosed. The disclosed method begins by providing a silicon substrate including a capping layer. A plurality of isolation trenches are then etched through the capping layer and into the silicon substrate to form a plurality of isolation regions in the silicon substrate. The isolation trenches are then filled with an oxide layer. The oxide layer and the capping layer are then polished back using techniques known in the art. After polishing, the semiconductor device is annealed between a temperature range of about 1150&deg; C. to about 1200&deg; C.

STI punch-through defects and stress reduction by high temperature oxide reflow process

A method for eliminating source/drain shorting generated during the highly-doped source/drain implant steps in a standard STI process is provided. This is achieved by reducing the RTA temperature to be less than 1000&deg; C. so as to minimize enhanced doping diffusion. Further, the energy level for the highly-doped source/drain implant steps is increased so to compensate for poly depletion in the gate electrodes.

Optimization of S/D annealing to minimize S/D shorts in memory array

A method of minimizing mechanical stress generated during the trench-forming/trench-filling process steps in a standard shallow trench isolation (STI) process is provided. This is achieved by forming trenches with a more sloped and smoother profile, and/or limiting the trench depth to be less than 0.4 &mgr;m, and/or reducing or increasing the trench densification temperature, and/or performing the densification step after the chemical-mechanical polishing step. In addition, a furnace TEOS oxide film is used as the trench-filling material.

Reduction of mechanical stress in shallow trench isolation process

An improved process of programming and erasing an EEPROM memory cell in an array of identical cells uses a reduced voltage on the write transistor of the cell to be programmed or erased and at the same time applies smaller voltages across the relatively thin oxides of the write transistors of the other cells in the array so as to reduce oxide leakage and damage in those cells but without disturbing the information stored in those cells. The result is the ability to scale down the size of the EEPROM memory cell allowing enhanced economies and permitting faster program, erase and reading speeds.

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Sunnyvale, CA, United States of America

Robert H Tu