Motorola Corporation

Robert H Reuss

David Joseph Monk

Curtis D Moyer

Changming Li

Mark S Birrittella

Christopher Paul Dragon

Jaynal Abedin Molla

Marc Kenneth Chason

Walter C Seelbach

Emmett Howard

Kevin L McLaughlin

Hang M Liaw

Steven A Voight

David W Jacobs

Babu R Chalamala

Peter A Smith

Jenny M Ford

Kathleen Anne Tobin

Kevin J Nordquist

Frederic B Shapiro

Lisa K Garling

Troy A Trottier

Ping Wang

Joseph Justin Bonanno

Diane A Carrillo

A field emission display ( ) includes a cathode plate ( ), an anode plate ( ), and a hydrogen source ( ), which is preferably disposed on cathode plate ( ) or anode plate ( ). Hydrogen source ( ) is distributed over the active area of field emission display ( ) and is made from a metal hydride, which is selected from the group consisting of titanium hydride, vanadium hydride, zirconium hydride, hafnium hydride, niobium hydride, and tantalum hydride. The metal hydride can be activated to provide an isotope of hydrogen in situ.

Field emission device having metal hydride hydrogen source

A vacuum gap dielectric field emission triode and a method of fabrication include a conductive layer positioned on a supporting substrate and an emitter positioned on the conductive layer. A gate metal layer electrically separated from the conductive layer defines a metal bridge gate surrounding the emitter and separated from the emitter by a substantially fixed distance. The gate metal layer defines a gate opening through the metal bridge gate overlying the emitter. An anode is positioned in spaced relationship to the gate metal layer and the triode is sealed in a substantial vacuum so that the emitter is separated from the metal bridge by the substantial vacuum and the metal bridge is separated from the anode by the substantial vacuum.

Method of manufacturing vacuum gap dielectric field emission triode and apparatus

A field emission device (100, 150) includes a cathode plate (102, 180) having electron emitters (116), an anode plate (104, 170) having a phosphor (107, 207, 307, 407) activated by electrons (119) emitted by electron emitters (116), and a vacuum bridge focusing structure (118, 158, 218, 318) for focusing electrons (119) emitted by electron emitters (116). Vacuum bridge focusing structure (118, 158, 218, 318) has landings (121, 122, 221, 322), which are attached to cathode plate (102, 180), and further has bridges (120, 220, 320), which extend above and beyond landings (121, 122, 221, 322, 421) to provide a self-supporting structure that is spaced apart from cathode plate (102, 180).

Field emission device having a vacuum bridge focusing structure and

A capacitor (100) includes first and second electrodes (102, 103) that each have an electroactive material (115, 120) disposed on a metallic substrate (105, 110). A solid electrolyte (125) including a polyacid is positioned between the first and second electrodes (102, 103). Polyacids are relatively low in cost, and their high ionic conductivity together with their thermal stability makes polyacids a viable alternative to solid polymer electrolytes.

Electrochemical capacitor with solid electrolyte

A capacitor (100) includes first and second electrodes (102, 103) an adhesive electrolyte (125) positioned therebetween. The adhesive electrolyte (125) includes an organic polymer and an inorganic component, which is either a polyacid or a polysalt.

Electrochemical capacitor with hybrid polymer polyacid electrolyte

An N-channel JFET (60) and a method of forming the N-channel JFET (60) in a BiCMOS process. The N-channel JFET (60) is monolithically fabricated with an N-channel IGFET (70), a P-channel IGFET (75), and an NPN BJT (80) in an epitaxial layer (21). The N-channel JFET (60) is formed in an isolated N-channel JFET region (24), the P-channel IGFET (75) is formed in an isolated P-channel IGFET region (27), and the NPN BJT (80) is formed in an isolated BJT region (29). The N-channel IGFET (70) is fabricated in a P-type well (26) that is not isolated from other N-channel IGFET's in the epitaxial layer (21). Accordingly, the N-channel JFET (60), the N-channel IGFET (70), the P-channel IGFET (75), and an NPN BJT (80) are monolithically formed in the BiCMOS process.

Method of forming a monolithic semiconductor integrated circuit having

A junction isolated P-well is formed for high performance BiCMOS. Two dopants of opposite conductivity types are implanted and co-diffused inside an annular N-type region to form a narrow N-type buried layer positioned between two P-type regions. N-type buried layer is formed having P-type doped regions above and below the N-type buried layer so that the N-type buried layer is narrow. The P-type region above the N-type buried layer provides for a retrograde profile of the P-well formed above it. Besides the P-well isolation, the P-type region below the N-type buried layer acts as a ground plane which collects noise, which helps to prevent it from being coupled to other devices of the BiCMOS circuit.

Isolated well and method of making

A transistor (10) is formed by utilizing an isolated well (18) within a thin epitaxial layer (14). A base mask (22) that has a base opening (23) is applied to expose a portion of the isolated well (18). A low resistance collector enhancement (24) is formed within the well (18) by doping a portion of the well (18) through the base opening (23). A base region (26) is formed overlying the collector enhancement (24) by doping the well (18) through the base opening (23). Forming the collector enhancement (24) through the base opening (23), facilitates providing the collector enhancement (24) with a small area thereby minimizing the transistor's (10) parasitic collector capacitance value, collector resistance, and transit time.

Forming a vertical PNP transistor

Method of forming isolated wells in the fabrication of BiCMOS devices

A method for making bipolar transistors with a first and a second buried collectors that are separated wherein the first and second buried collectors are separated by a p buried layer that is made by depositing a heavily doped boron layer and subsequently diffusing boron from the boron layer into the area between the first and second buried collector.

Method for making buried isolation

A low capacitance, high performance semiconductor device is described having a sidewall emitter wherein the emitter width is relatively small (approximately 0.5 micrometers). This enables a small emitter-base interface which reduces capacitance. Additionally, the regions of the base and collector near their interface are lightly doped so that collector-base capacitance is greatly reduced.

Vertical semiconductor device having a sidewall emitter

Improved bipolar transistors having minimum base-collector and collector-substrate junction area are formed by using multiple polycrystalline (e.g. doped poly silicon) layers to make lateral contact to a pillar shaped single crystal device region. The lateral poly silicon contacts are isolated from each other and the substrate and extend to the upper surface of the device for external connections. The structure is made by depositing two dielectric-poly layer sandwiches, etching and oxidizing part of the poly silicon layers to provide isolated overlapping poly silicon regions, etching a first hole through both poly silicon regions to the substrate, etching a second hole to the lower poly silicon layer, and filling the first and second holes with single and poly-crystalline silicon, respectfully. A sidewall oxide is formed at the periphery of the top of the single crystal pillar for defining the emitter location without additional masking.

Method of forming transistors with poly-sidewall contacts utilizing

An integrated circuit power supply interconnection technique is disclosed having a highly doped, low resistivity substrate for distribution of the integrated circuit's most positive supply voltage. The substrate functions as the most positive voltage point and accomodates devices that are normally connected directly to this most positive supply voltage. A dielectric buried layer overlies a portion of the substrate and isolates the substrate supply voltage from devices that are not connected directly to the most positive supply voltage.

Growing community of inventors

Scottsdale, AZ, United States of America

Robert H Reuss