Hewlett-packard Company

Agilent Technologies, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Other

Avago Technologies General IP Pte, Ltd.

Avago Technologies Enterprise IP (singapore) Pte. Ltd.

Robert H Miller, Jr

Craig A Heikes

Jeffry D Yetter

Glenn T Colon-Bonet

Robert James Martin

David R Smentek

Samuel D Naffziger

Jade M Kizer

Brian C Miller

Edmundo Rojas

Robert M Thelen

Gilbert Yoh

Roger W Swanson

Darrin C Miller

Hui-Sian Ong

John R Spencer

Rodolfo G Beraha

Rudolfo G Beraha

A receiver termination circuit includes an internal AC coupling capacitor and an adjustable resistor forming an adjustable high-pass filter (HPF) at a receiver side of a transmission medium, and a digital-to-analog converter (DAC) coupled to the adjustable HPF, the DAC configured to provide a signal having a low-pass filter response to the adjustable HPF to provide a DC restore function.

System and method for internal AC coupling with active DC restore and adjustable high-pass filter for a PAM 2/4 receiver

An apparatus for generating a constant logical value in an integrated circuit includes a first logic network having n outputs, the n outputs providing 2possible output combinations, where the n outputs assume a state that is a subset of the 2possible output combinations and a second logic network configured to generate at least one constant logic signal when the n outputs assume any state that is part of the subset of the 2possible output combinations.

Apparatus and method for generating a constant logical value in an integrated circuit

A random noise signal generator circuit comprising a random noise source that produces a random noise signal, an amplification circuit that amplifies the random noise signal to produce an amplified random noise signal, a feedback loop having a DC offset correction circuit, and a summer. The DC offset correction circuit processes a fed back portion of the amplified random noise signal to produce a DC offset correction signal. The summer sums the random noise signal produced by the random noise source and the DC offset correction signal to produce a summed signal. The summer is electrically coupled to the amplification circuit for providing the summed signal to the amplification circuitry. The amplification circuitry amplifies the summed signal to produce a random noise output signal.

Random noise generator and a method for generating random noise

A frequency divider apparatus is a closed loop system of a recirculating memory element, at least one feedback memory element and an end memory element in series combination. Each memory element accepts a common clock. An end memory element output is logically combined with at least one of the other memory element outputs and provides an input to the closed loop system to generate a self-initializing state machine.

Self-initializing frequency divider

An apparatus has a frequency divider accepting a clock. The frequency divider is selectable between an N divide factor and an M divide factor via a divide mode signal, where an absolute value of (N&#x2212;M)=1. The apparatus also has a pulse generator responsive to a slip signal and driven by an output of the frequency divider and providing the divide mode signal to the frequency divider.

Frequency divider with slip

A method and apparatus for operating a memory is presented. Information is stored in the memory based on a first time domain and information is read from the memory based on a second time domain. A cooperative relationship is maintained between a write pointer which points to memory locations, where data will be stored and a read pointer which points to memory locations, from which data will be read. A FIFO memory is presented which has memory locations and a register array is presented which stores a bit array that has bit locations. Each bit location in the bit array corresponds to a memory location in the memory. As the write pointer points to a memory location and data is stored in the memory location, a bit (e.g. flag) is set in the bit array. The Flag designates whether the data stored in the memory location is available for reading. Prior to reading information from the memory location, a test is made of the bit location that corresponds to the memory location. The bit value denotes whether the data stored in the memory location is valid data and available for reading.

Method and apparatus for asynchronous read control

A method and circuit is presented for generating a random bit stream based on thermal noise of a Complementary Metal Oxide Semiconductor (CMOS) device. A circuit implementing the invention preferably includes at least a pair of identically implemented thermal noise generators whose outputs feed a differential amplifier. The differential amplifier measures and amplifies the difference between the noise signals. A sampling circuit compares the difference with a threshold value that is selected to track with process/voltage/temperature variations of the noise generator circuits to output a binary bit having a bit value determined according to the polarity of the noise difference signal relative to the threshold value. The sampling circuit may be clocked to generate a random bit stream.

Random bit stream generation by amplification of thermal noise in a CMOS process

A series of logic clouds is used to distribute and propagate signals traveling a relatively long distance across a data logic circuit fabric. One or more long distance signals originate from an initial logic cloud that may be located on a source data block and pass through a series of logic clouds that may be located on an intermediate data block before passing through a destination logic cloud located on a destination data block. Each logic cloud reads both stabilized logic signals and long distance signals and employs a NAND gate connected with an inverter to perform not only logical operations but also to act as a repeater between the logic clouds. The stabilized logic signals may represent signals that originate from other sources along a given data path.

Method and apparatus for low latency distribution of logic signals

An input number is applied to a look-up table that supplies three coefficients based upon certain bits of the input that define a series of bins. The first coefficient is fed directly to an adder that produces the output. The second coefficient is multiplied by a number corresponding to how far the input is from the edge of a bin. This number is then input to the adder that produces the output. The third coefficient is multiplied by a number that is the result of a curve-fit function of a number corresponding to how far the input is from the middle of a bin. This result is then input to the adder that produces the output. These three addends are aligned and summed to produce an output that corresponds within a certain precision of a chosen mathematical function of the input such as the mathematical inverse (1/x) or the mathematical inverse of the square root of the input.

Function generating interpolation method and apparatus

A bit position, M, that determines the accuracy and efficiency of the approximation is selected from an N bit binary number. The multiplicand is generated by removing the Mth bit from the binary number, shifting the bits of lower order than the Mth bit up on position, then filling the lowest order bit with a zero. The multiplier is generated by removing the Mth bit, and all lower order bits from the binary number. Booth's algorithm is then used to multiply the multiplicand and the multiplier except that the Mth bit is used instead of an assumed zero during the first step of the multiplication. In hardware, a partial Booth-encoded multiplier is used to produce and approximate square of a binary number. For an N bit number, and a selected bit in the Mth position, the partial Booth-encoded multiplier has N columns, and N&minus;M rows and N&minus;M booth encoders. The inputs to the columns are wired so that the multiplicand has the Mth bit from the binary number removed and the bits of lower order than the Mth bit up are shifted up position, the lowest order bit being filled with a zero. The inputs to the Booth encoders are the N&minus;M highest order bits of the binary number. The Mth bit of the binary number is input to the first Booth encoder instead of an assumed zero.

Method and apparatus for efficient calculation of an approximate square of a fixed-precision number

A system and method for transferring data between alternately evaluated first and second logic blocks of a dynamic logic pipeline. Associated with the system and method is a transparent data-triggered pipeline latch for controlling data flow between the first and second logic blocks. During an evaluation period accorded the first logic block, data existing at the logic block's data inputs is evaluated. Substantially simultaneously, the data-triggered latch is reset. As valid data is output from the first logic block, the latch is triggered. Immediately after the latch has been triggered, and before a clock-triggered evaluation period is accorded the second logic block, the data stored in the latch is output to the second logic block. Propagation of the early arriving data may be halted by ANDing the early arriving data signals with clocked signals which remain invalid. The invalid signals may comprise clock or data signals. Early arriving data is beneficial when supplied to static logic gates, or when transmitted through heavily loaded data lines which are associated with a propagation delay. A preferred embodiment of the latch comprises high and low level mousetrap data controls. Each control is coupled with a respective high or low level mousetrap data input, output, and storage node, and further comprises an input trigger, an input trigger disabler, a data storage device, a reset mechanism, and a reset disabler. The latch allows data to be driven out when valid, rather than in response to a clock edge.

Transparent data-triggered pipeline latch

Improved and less complicated leading bit anticipation (LBA) for a PKG floating point adder of n-bit 2's complement operands is accomplished by representing de-normalized (n+1)-bit operands as (n+1)-many PKG symbols. These are grouped into (n-1)-many triples, each of which has two adjacent PKG symbols in common with its neighboring triple. Presuming the existence of a least significant PKG symbol of K allows the formation of an additional triple of lesser significance. Each triple produces an associated transition bit that when set indicates, for the partial summation segment of the raw sum of bit location corresponding to the location of the triple, if the left-most two bits of the corresponding partial summation segment are, or would be with a carry-in, of opposite bit values. The bit position of the most-significant set transition bit is determined in terms of how many bit positions J that is from the most significant transition bit position. The raw sum is normalized by shifting it left by J-many bit positions and adjusting its exponent by J. If J is one too low in value then the raw sum is shifted and its exponent is adjusted by one extra count. When no transition bits are set, the raw sum is zero. A raw sum of zero does not need normalization, although the zero case needs to cause a forced a zero for the exponent. If a slightly different rule is used for determining the transition bit of the MSB, then a simplification of the rule for producing transition bits for all remaining bit positions is possible. That simplification is that any triple whose center symbol is P can produce an associated transition bit of zero.

Leading bit anticipator

A method and apparatus for determining the trailing bit position from a two operand addition is described. The determination of the trailing bit occurs in parallel with the addition. The two operands are encoded together and the encoded word used to determine the trailing bit position. As the operations of encoding the operands and operating upon the encoded operands require no more time than known methods to determine the trailing bit position after the addition is completed, and as the encoding and operating on the encoded words occurs in parallel with the addition operation, the present invention allows faster processing in the floating point unit.

Trailing bit anticipator

An apparatus and method are disclosed for regulating power consumption in a digital system of the kind including at least one triggerable functional block that consumes more power when triggered than when not triggered. In an embodiment for use with a digital system that includes a pipeline of such triggerable functional blocks, a state machine sequentially applies trigger pulses to each of the functional blocks in the pipeline whenever the output of an OR gate is asserted. It does so by generating a series of enable signals that are used to gate a clock signal to the trigger inputs of the functional blocks. The state machine includes a series of storage devices having outputs. Outputs of the storage devices are used to provide the enable signals. The inputs of the OR gate are coupled to a start signal that indicates when the functional blocks should be triggered to process data, and also to a dummy start signal that indicates when the functional blocks should be triggered to maintain power consumption. Outputs from the storage devices are also used to indicate the number of times the pipeline has been triggered during a recent number of clock cycles. A programmable register is used to store a data value corresponding to the minimum desired level of power consumption for the pipelined functional blocks. The dummy start signal is generated by combinational logic whose inputs include the outputs of the storage devices and the data value. Because the minimum desired level of power consumption may be programmed by the user, thermal characterization and balancing of step load with average power are facilitated.

Apparatus and method for regulating power consumption in a digital system

The operation of a pipeline is observed by launching two or more sets of data into the pipeline on consecutive clock cycles. The clock free-runs for as many cycles as it takes the data to propagate through the stages of the pipeline. The output latches of each stage of the pipeline are only sampled when the data of interest is held in each output latch, respectively. Observation may be completely controlled through a standard test access port (TAP). Observation may be accomplished by halting the clock to scan new data in and results out, or with the clock free-running. The inputs to the pipeline may come from test registers or from circuitry which feeds the pipeline during normal operation.

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Loveland, CO, United States of America

Robert H Miller, Jr