California Institute of Technology

Other

Robert H Lin

Goutam Chattopadhyay

Choonsup Lee

Imran Mehdi

Alejandro Peralta

Ken B Cooper

Cecile D Jung-Kubiak

John J Gill

Theodore J Reck

Jose Vicente Siles Perez

Jose V Siles

Risaku Toda

Bertrand Thomas

Emmanuel Decrossas

Erich T Schlecht

Sofia Rahiminejad

Sven L Van Berkel

Seth Sin

Low-loss terahertz switches with nanometer resolution positioning and feedback are disclosed. In one embodiment, the switch uses a U-bend waveguide surrounded by an electromagnetic band gap and is implemented in a fully metal-machined fashion in combination with a piezo-electric motor and an optical linear encoder. In another embodiment, the switch comprises a MEMS device.

Terahertz waveguide switches

A solid-state device chip including diodes (generating a higher or lower frequency output through frequency multiplication or mixing of the input frequency) and a novel on-chip diplexing design that allows combination of two or more multiplier or mixer structures operating at different frequency bands within the 50-5000 GHz range within a same chip and/or waveguide. The on-chip diplexing design consists of a single-substrate multiplier chip with two or more multiplying structures each one containing 2 or more Schottky diodes. The diodes in each structure are tuned to one portion of the target frequency band, resulting in the two or more structures working together as a whole as a large broadband multiplier or mixer. Thus, an increase in bandwidth from 10-15% (current state-of-the-art) to at least 40% is achieved. Depending on the target frequencies, each subset of diodes within the chip can be designed to work either as a doubler or a tripler.

On-chip diplexed multi-band submillimeter-wave/terahertz sources

A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

Wafer-to-wafer alignment method

A solid state device chip including diodes (generating a higher frequency output through frequency multiplication of the input frequency) and a novel on-chip power combining design. Together with the on-chip power combining, the chip has increased efficiency because the diodes' anodes, being micro-fabricated simultaneously on the same patch of a GaAs wafer under identical conditions, are very well balanced. The diodes' GaAs heterostructure and the overall chip geometry are designed to be optimized for high power operation. As a result of all these features, the device can generate record-setting power having a signal frequency in the F-band and W-band (30% conversion efficiency).

High power W-band/F-band Schottky diode based frequency multipliers

A multi-pixel terahertz transceiver is constructed using a stack of semiconductor layers that communicate using vias defined within the semiconductor layers. By using a stack of semiconductor layers, the various electrical functions of each layer can be tested easily without having to assemble the entire transceiver. In addition, the design allows the production of a transceiver having pixels set 10 mm apart.

340 GHz multipixel transceiver

A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

Silicon alignment pins: an easy way to realize a wafer-to-wafer alignment

A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.

Multi-step deep reactive ion etching fabrication process for silicon-based terahertz components

A method for automatically testing an apparatus controlled by software based on pilot test case file comprising user input sequence data recorded manually and the time stamp of the input. In the process of automated testing, these pre-recorded user inputs are replay with same input sequence but with either the same time interval between two subsequent inputs recorded prior; or with a random time interval autonomously generated in a range set by the test configuration. During the process of replaying user input, a separate plural numbers of background tasks are executed in parallel with random execution delays to generate varying system load and execution timing to simulate the apparatus' unpredictable real operation scenarios. The user input and new random time interval between each user input are recorded at replay as a new expanded test record file for later test result trace and failure analysis.

Self-expanding test automation method

A coplanar waveguide (CPW) based subharmonic mixer working at 670 GHz using GaAs Schottky diodes. One example of the mixer has a LO input, an RF input and an IF output. Another possible mixer has a LO input, and IF input and an RF output. Each input or output is connected to a coplanar waveguide with a matching network. A pair of antiparallel diodes provides a signal at twice the LO frequency, which is then mixed with a second signal to provide signals having sum and difference frequencies. The output signal of interest is received after passing through a bandpass filter tuned to the frequency range of interest.

Growing community of inventors

Chino, CA, United States of America

Robert H Lin