Bell Telephone Laboratories

At&t Bell Laboratories

Robert H Krambeck

Masakazu Shoji

John A Copeland, Iii

James A Cooper, Jr

Carlo Heinrich Sequin

Robert Henry Walden

Sung M Kang

An op-amp feedback arrangement is used to provide non-skewed clock pulses from a source of skewed clock pulses. Any skew in the clock-in pulses results in a change in the average voltage of a clock-out pulse at the output of the arrangement. The average voltage of the clock-out pulse is compared to a reference voltage to produce a control signal which adjusts the average voltage at the output. Critical transitions in the clock pulses occur at precise time relationships under the control of the control signal.

Skew-free clock circuit for integrated circuit chip

A circuit for rotating a multibit binary word in either the right or the left direction includes a scale factor decoder receiving a scale factor word which specifies the magnitude of the rotation and a direction control signal which specifies the direction of rotation and providing a shift control word which is the same as the scale factor word when a right rotation is specified but providing a shift control word which is the complement of the scale factor word when a left rotation is specified. The circuit also includes a plurality of input buffers receiving an input word and providing corresponding input data, and a one-bit rotator receiving the input data and the direction control signal and rotating the input data in the right direction by one position when a left rotation is specified or providing the input data without rotation when a right rotation is specified. In addition, the circuit includes a network receiving data from the one-bit rotator and the shaft control word and rotating the data from the one-bit rotator in only the right direction by a magnitude specified by the shift control word. Furthermore, the circuit includes a plurality of output buffers receiving the data from the network and providing an output word.

Data shifting and rotating apparatus

Logic circuits, particularly of the integrated semiconductor type, are accessed at improved speeds by preventing pull-ups from occurring during the access time and by the inclusion of on-chip delay circuitry to avoid switching later stages in a manner to lose information while output nodes of earlier stages are high. All stages are activated in response to a single clock pulse edge.

Multistage logic circuit arrangement

The numbers of gates necessary in an integrated combinatorial logic circuit is reduced by designing the circuit to accept an applied binary word of given length as a plurality of word segments having numbers of bits which add up to the number included in the applied word. A preprocessor responds to the word segments to generate a word characterizing the segments and to apply those words to an arithmetic logic unit designed to add binary words and to generate words having lengths of the applied words.

Circuit for determining the number of ones in a binary signal

Charge transfer devices which permit movement of charge carriers in two noncollinear directions in the surface plane of the device. A network of electrodes in two levels of metallization is combined with an appropriate doping of the storage medium to define the charge transfer paths. The direction of charge transfer is determined by an appropriate pulsing of the network which may take the form of different driving sequences of a number of phases in various embodiments. This concept may be used for both charge coupled and bucket brigade devices.

Two-dimensional transfer in charge transfer device

This invention furnishes a semiconductor shift register circuit characterized in that each stage of the register contains a dynamic 'master' portion feeding a static 'slave' portion. The register circuit is driven by a suitable clock voltage circuit such that if the signal source for the clock circuit should stop, then the information in each stage is retained and is stored in the static portion. In this way, the overall performance of the shift register is static in the sense that the information in the register is not lost during temporary stoppage of the driving clock; yet, fewer electrical component elements are required per entire stage than in the case of a fully static stage.

Functionally static type semiconductor shift register with half

In a semiconductor charge transfer device circulating memory, the input control circuit to the device has the capability of either allowing the previous stream of charge packets either to continue circulating as the same information or of modifying the stream in accordance with a 'write data' external signal, as each circulating bit passes from the output to the input charge storage site of the semiconductor charge transfer device. This invention involves the use of appropriately located integrated circuit transistor means for draining off excess electrical charges which have been found to accumulate at certain terminals in the input circuit, in order to suppress spurious error signals otherwise generated by these excess charges.

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Warren, NJ, United States of America

Robert H Krambeck