Texas Instruments Corporation

Robert H Eklund

Robert H Havemann

David B Spratt

Eldon J Zorinsky

Robert L Virkus

Scott H Prengle

Leo Stroth

Ravishankar Sundaresan

David Barry Scott

Roger A Haken

Gordon P Pollack

Clyde R Fuller

Douglas A Prinslow

Dave Monahan

A method of forming an integrated circuit device including at least one polysilicon resistor,is disclosed herein. A polysilicon layer,is formed, possibly over a field oxide,. The polysilicon layer,is then doped to achieve a selected sheet resistance. An insulating layer,(e.g., an oxide, a nitride, or a combination thereof) is then formed over the polysilicon layer,. The insulating layer,is patterned and etched to define a resistor body,in the underlying polysilicon layer,. The polysilicon layer,is then patterned and etched to define first and second resistor heads,abutting the resistor body,while simultaneously at least one polysilicon element,of a second electronic device is formed. Other systems and methods are also disclosed.

Process of making polysilicon resistor

A BiCMOS structure and a method for making the same is disclosed, where the dielectric layer between the emitter electrode and the base region is formed of a deposited dielectric. After definition of the bipolar and MOS moat regions, a layer of polysilicon is deposited thereover, and removed from the bipolar region. The base implant is performed either prior to or after the etch of the polysilicon layer. A layer of TEOS oxide is formed thereover and is etched to remain in portions of the bipolar region, with an emitter contact formed therethrough and a portion of the bipolar region exposed at which the extrinsic base is formed. An alternative embodiment of the invention includes scaling the emitter contact by forming sidewall oxide filaments therewithin. A second layer of polysilicon is disposed thereover to form the emitter electrode, and to merge with the first layer to form the gates of the MOS transistors. Subsequent patterning and etching of the polysilicon, followed by sidewall filament formation and source/drain doping, is performed to complete the structure.

Integrated circuit structure having a bipolar transistor with a thick base oxide and a field effect transistor with a thin gate oxide

The present invention is a method for improving transistor channel hot carrier reliability by incorporating a solid deuterium source into the transistor structure. This is accomplished by using a deuterium containing source gas for formation of components of the transistor structure. A deuterium sinter, shown to improve channel hot carrier lifetime, is made a more viable process step by using deuterium as a source gas for formation of components made of silicon nitride. Additionally, time and/or temperature of the sinter may reduced. Incorporation of deuterium containing components which allow sufficient outdiffusion of deuterium may eliminate the need for a final deuterium sinter.

Transistor structure incorporating a solid deuterium source for gate

Method for forming a thick base oxide in a BiCMOS process

A merged BiCMOS device 10 having a bipolar transistor 60 and a PMOS transistor 64 formed in the same well region 18. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18. Emitter electrode 30 is separated from base region 26 by thick oxide 24. Tungsten-silicide layer 32 covers emitter electrode 30. PMOS transistor 64 comprises source/drain regions 52 and 52a, gate electrode 40, and gate oxide 36. PMOS transistor 64 may optionally comprise LDD regions 44. Source/drain region 52a is in contact with base region 26. If desired, the emitter electrode 30 and gate electrode 40 may be silicided.

Bi-CMOS merged devices

A polysilicon resistor (40) includes a field oxide layer (12) and a polysilicon layer (20) that covers a portion of field oxide layer (12). The polysilicon layer (20) possesses a predetermined electrical resistance value. Nitride/oxide stack (42) covers a predetermined portion of the polysilicon layer (20) and forms at least one exposed location of polysilicon layer (20) on which not to implant a dopant to achieve a predetermined resistance value. Silicide layer (34) covers exposed location.

Method of forming a polysilicon resistor using an oxide, nitride stack

A merged BiCMOS device 10 having a bipolar transistor 60 and a PMOS transistor 64 formed in the same well region 18a. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18b. Emitter electrode 30 is separated from base region 26 by thick oxide 24. PMOS transistor 64 comprises source/drain regions 52 and 52a, gate electrode 40, and gate oxide 36. PMOS transistor 64 may also comprises LDD regions 44. Source/drain region 52a is in contact with base region 26. If desired, the emitter electrode 30 and gate electrode 40 may be silicided.

Bicmos process that supports merged devices

A BiCMOS device 10 having a bipolar transistor 60, a PMOS transistor 64 and a p-type polysilicon resistor 70. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18. PMOS transistor 64 comprises source/drain regions 52, gate electrode 40, and gate oxide 28. PMOS transistor 64 may also comprises LDD regions 44. The emitter electrode 30 and gates 40 are formed out of the same polysilicon layer and thus have the same thickness. If desired, the emitter electrode 30 and gate electrodes 40 may be silicided.

BiCMOS process with surface channel PMOS transistor

An integrated circuit device including at least one polysilicon resistor 10 is disclosed herein. A polysilicon layer 24 is formed, possibly over a field oxide 12. The polysilicon layer 24 is then doped to achieve a selected sheet resistance. An insulating layer 18 (e.g., an oxide, a nitride, or a combination thereof) is then formed over the polysilicon layer 24. The insulating layer 18 is patterned and etched to define a resistor body 14 in the underlying polysilicon layer 24. The polysilicon layer 24 is then patterned and etched to define first and second resistor heads 16 abutting the resistor body 14 while simultaneously at least one polysilicon element 28 of a second electronic device is formed. Other systems and methods are also disclosed.

Polysilicon resistor structure including polysilicon contacts

BiCMOS process for supporting merged devices

This is a method of fabricating a transistor on a wafer. The method comprises: forming a doped silicon layer; patterning the active transistor regions of the doped silicon layer and utilizing a silicon etch to remove the non-transistor regions of the doped silicon layer to create a silicon mesa; forming a gate oxide layer on a doped silicon mesa; depositing a polysilicon layer on top of the oxide layer; depositing a photoresist layer over the polysilicon mesa; patterning the photoresist layer with a gate configuration; etching to remove portions of the polysilicon layer using the photoresist as a mask to create a polysilicon gate; depositing a TEOS layer over the polysilicon gate and exposed gate oxide; etching to remove portions of the TEOS layer and the exposed gate oxide to leave sidewall spacers on sides of the polysilicon gate and sides of silicon mesa; depositing a metal layer over remaining portions of the polysilicon gate, the sidewall spacers, and the silicon mesa; annealing the wafer to react portions of the metal layer with exposed portions of the silicon mesa to form a metal silicide; etching all unreacted the metal layer to leave the silicided portions of the polysilicon gate and silicided portion of the doped silicon layer.

Method of making a thin film transistor

BiCMOS process that supports merged devices

This invention is a silicon bipolar integrated circuit comprising: a high barrier Schottky diode clamp on a bipolar transistor, the diode clamp comprising a self-aligned PtSi layer on a silicon surface; and a TiN local interconnect partially overlying the PtSi layer. It also is a method of manufacturing an integrated circuit comprising: forming a self-aligned PtSi layer on the adjacent base and collector silicon regions, the PtSi serving as a clamp diode on the bipolar transistor; and forming an etch-patterned TiN layer partially overlying the PtSi layer, the etch-patterned TiN layer serving as local interconnects. The invention provides a PtSi Schottky diode on a bipolar transistor in combination with a TiN local interconnect with the advantages of (i) providing a TiN local interconnect which can be etched without also etching the PtSi, (ii) permitting a wide process window for overetching at contacts, (ii) a TiN local interconnect which is an improvement over a polysilicon local interconnect, and (iv) a high barrier Schottky diode for clamping a bipolar transistor.

Process for obtaining high barrier Schottky diode and local interconnect

Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions. The collector contact region is self aligned to the second sidewall oxide spacer which prevents the contact of base and heavily doped collector. Finally, the oxide cap covering the upper emitter surfaces is removed and emitter, base and collector contact regions are silicided to reduce contact resistance.

Method of forming a recessed contact bipolar transistor

This invention is an SOI BICMOS process which uses oxygen implanted wafers as the starting substrate. The bipolar transistor is constructed in two stacked epitaxial layers on the surface of the oxygen implanted substrate. A buried collector is formed in the first epitaxial layer that is also used for the CMOS transistors. The buried collector minimizes the collector resistance. Selective epitaxial silicon is then grown over the first epitaxial layer and is used to form the tanks for the bipolar transistors. An oxide layer is formed over the base to serve as an insulator between the emitter poly and the extrinsic base, and also as an etch stop for the emitter etch. The emitter is formed of a polysilicon layer which is deposited through an opening in the oxide layer such that the polysilicon layer contacts the epitaxial layer and overlaps the oxide layer.

Growing community of inventors

Plano, TX, United States of America

Robert H Eklund