Honeywell G.m.b.h.

Concord Communications, Inc.

Robert H Douglas

Robert J Handly

Thomas L Phinney

Edward H Forrester

David Murray

The invention is a network monitor that passively detects sequences of control frame transmissions. Detected control frame sequences are compared to a model of the expected exchange of control frames. The monitor concludes that a malfunction has occurred when the detected control frame sequences do not match the frame sequences indicated by model. The monitor is quite useful with a network that uses a token passing protocol, since it can determine whether a particular station is working improperly by tracking whether the token is passed in the order proscribed by the expected token-passing sequence in the model. The monitor can detect and diagnose many types of network malfunctions. The monitor also observes and maintains statistics on network data traffic and configuration information, in real time. Since the monitor independently tracks which station has the token, statistics are developed on how much traffic is passing to and from bridges.

Passive monitor for broadcast communication network

A computer system includes a main memory and a cache memory arrangement, wherein a cache memory unit is associated with each of the several CPU's in the system. Each cache responds to the virtual address signals issued by the associated CPU, in parallel with a mapper unit which, in turn, converts the virtual address signals to physical address signals for addressing the main memory. The cache is subdivided into subunits each responding to a particular program of a multiprogram CPU. When any of the CPUs address a shared portion of the main memory, the mapper unit recognizes the address of the shared portion of the main memory and issues an inhibit signal to inhibit the operation of the cache memory unit to prevent data from the shared portion of the main memory from being stored in the cache.

Virtual cache

An improved means and method for accomplishing floating point calculations in computational apparatus includes a primary microprocessor and a secondary microprocessor each with its own control ROM. The normal or fixed point calculations are handled by the primary microprocessor under the control of a first segment of the associated control ROM. When a floating point calculation is called for, a second segment of that ROM is addressed. The addressing of the second segment of the first ROM also effects the coincident addressing of the ROM of the secondary microprocessor. For floating point calculations, the exponent portion of the numbers being manipulated is handled in the primary microprocessor. Simultaneously therewith, the mantissa portion of the numbers being manipulated are handled in the secondary microprocessor under the control of its associated control ROM. The resultant calculations are recombined in the primary microprocessor to produce a complete solution for the floating point calculation.

Floating point arithmetic control

There is provided, in accordance with the present invention, apparatus comprising a shared random access memory in which is stored requests for access to data in a bulk memory unit. The data being stored in redundant storage areas and the requests stored in the RAM include the address of the redundant data. Means are provided for determining if that data request is already in progress through one of the redundant addresses. The first of the addresses accessed causes the others to be blocked to prevent multiple accessing of the same data. The checking and selection is accomplished by high speed logic circuitry.

Read request selection system for redundant storage

There has been provided, in a computer system, a control unit having authority over a plurality of subordinate units with differing response times. The control unit addresses and issues command instructions to selected ones of the subordinate units then waits for an acknowledgement of completion from the addressed units before going to the next step in its routine. To prevent the control unit from being hung-up in the event of a failure of response from the subordinate unit, time-out means are provided for releasing the control unit for further operation. Since the response times of the individual subordinate units are unknown to the control unit, a unique time-out circuit is provided for each of the subordinate units, each time-out circuit being commensurate with the response time of the associated subordinate unit.

Time-out interface means

A computer system features a processor unit which includes its own microprogram control unit. The microprogram control unit includes a storage means for operational instructions for the processor unit and means to issue those instructions in a desired sequence. A communication Bus provides communication channels between the processor unit and either data storage means or other processor units served by the Bus. The processor unit includes a number of clock controlled functional components as well as means for requesting access to the Bus. A clock signal generating means is controlled by signals from the microprogram control unit. When a request has been made for access to the Bus, the processor continues to operate until a point is reached when access to the Bus must be accomplished before continuing. The microprogram control unit issues a control signal which effectively stops the operation of the clock signal generating means until the Bus access routine has been accomplished. The clock signal generating means resumes operation when the access routine has been completed.

Microcomputer apparatus

A computer apparatus includes means for comparing the address stored in an address register with a preset address. When the stored address matches the preset address the comparison means issues an alarm signal which may be used to effect an immediate halt in the execution of a routine, trigger suitable annunciators or, selectively, to enable the injection into the routine of an overriding preset instruction.

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Phoenix, AZ, United States of America

Robert H Douglas