Integrated Device Technology, Inc.

Synaptics Corporation

Adva Optical Networking Se

Robert H Bishop

Angus David Starr MacAdam

Bruce Lorenz Chin

David Dworkin

Prashant Shamarao

Brian Scott Darnell

David J Klein

Bruce C Grugett

Chris DeMarco

Rohit Singhal

Alex Reed

Marshall Johnson

Frank D Matthews

An apparatus comprising high speed ports connected via an integrated high speed serial switch fabric and serializer/deserializer circuits to an internal processing logic, wherein the high speed serial switch fabric is adapted to switch a serial reception signal received by a high speed port to at least one of at least one other high speed port of the apparatus and to the serializer/deserializer circuit of the receiving high speed port.

Using SerDes loopbacks for low latency functional modes with full monitoring capability

An AUX channel amplifier for amplifying data in the AUX channel of a Display Port device. In some embodiments, the amplifier includes a first amplifier coupled to amplify a signal from a source to a sink and a second amplifier coupled to amplify a signal from the sink to the source. A slicer can be utilized to digitize the signal from the source. In some embodiments, a clock and data recovery can be utilized to receive signals from the source and a second clock and data recovery can be utilized to receive signals from the sink. A controller determine the direction of data flow and enables the first amplifier or the second amplifier accordingly.

Bi-directional channel amplifier

A packet switch includes virtual output queues for mapping data units of data packets from input ports to output ports of the packet switch. The packet switch selects virtual output queues based on old age indicators of the virtual output queues and routes data units mapped at heads of the selected virtual output queues to output ports of the packet switch. Further, the packet switch may identify a data unit of a multicast data packet mapped at the head of more than one virtual output queue and contemporaneously route the data unit to more than one output port. Additionally, the packet switch may update an old age indicator to indicate a virtual output queue is old if the virtual output queue maps an unserviceable data unit of a multicast data packet and the same data unit is mapped at the head of a selected virtual output queue.

Old virtual queues technique for routing data packets in a packet switch

A communication system includes a packet switch that routes data packets between endpoint devices in the communication system through virtual channels. The packet switch includes output ports each having a link bandwidth for outputting data packets. Each virtual channel is associated with an output port and is allocated a portion of the link bandwidth of the output port. The packet switch receives a data packet identifying a virtual channel at an input port, selects another virtual channel associated with the input port, routes the data packet through the packet switch, and outputs the data packet from the packet switch by using the selected virtual channel. Additionally, the packet switch may select a reliable transmission protocol, a continuous transmission protocol, or a pseudo-continuous transmission protocol for outputting the data packet from the packet switch. In some embodiments, the packet switch modifies the data packet to indicate the selected virtual channel.

Packet switch with configurable virtual channels

A packet switch including input ports and output ports allocates an output bandwidth of each output port among virtual channels based on bandwidth allocations values corresponding to the virtual channels and a bandwidth precision value of the output port. The bandwidth precision value indicates a number of bandwidth precision bits, which may be outside a bandwidth reservation precision range specified in a serial RapidIO standard. The packet switch receives data packets compliant with the serial RapidIO standard at the input ports, identifies an output port for each data packet, and selects input ports based on the output ports of the data packets. Further, the packet switch routes a data packet from each selected input port to the output port of the data packet, and the output port outputs the data packet by using the output bandwidth of the output port allocated to the virtual channel identified by the data packet.

Packet switch with configurable bandwidth allocation precision

A grid array microelectronic package includes a substrate and an array of external connectors on the substrate that are arranged in rows and columns to define a periphery of the array and the interior of the array. A routing channel is provided in the array that increases the periphery of the array by at least four external connectors, compared to absence of the routing channel. The routing channel may be made of two missing external connectors, at least two strapped external connectors and/or at least two 'no-connect' external connectors in the array that extend from the periphery of the array towards the interior of the array. Signal conductors may extend along the routing channel.

Grid array microelectronic packages with increased periphery

A First-In-First-Out (FIFO) memory device includes a FIFO memory block, a data input interface that writes data into the FIFO memory block in synchronization with a first clock, and a data output interface that reads the data from the FIFO memory block in synchronization with a second clock. The data input interface provides a first indication to the data output interface that the received data has been written into the FIFO memory block. The first indication persists until reset by the data output interface. The data output interface provides a second indication to the data input interface that the received data has been read from the FIFO memory block. The second indication persists until reset by the data input interface.

Asynchronous FIFO increment and decrement control for interfaces that operate at differing clock frequencies

Preferred memory devices include a first bit line within a first block of memory and a second bit line within a second block of memory. The first bit line is electrically coupled to a reference voltage signal line by a pull-up transistor that turns on in response to an active first bit line pull-up signal (e.g., /BLPU_IOn&equals;0). The second bit line is also electrically coupled to the reference voltage signal line by a pull-up transistor that turns on in response to an active second bit line pull-up signal (e.g., /BLPU_IOn&plus;1&equals;0). A control circuit is provided and this control circuit is responsive to a multi-bit shift signal. The control circuit disables generation of the active first bit line pull-up signal in favor of an active second bit line pull-up signal when a value of the shift signal designates replacement of the first block of memory with the second block of memory. The control circuit may also generate signals that disconnect a first IO line associated with a defective first block of memory and substitute a second IO line associated with a functional second block of memory for the first IO line.

Integrated circuit memory devices having control circuits therein that provide column redundancy capability

A priority encoding interface transmits data to the receiving device from a highest priority FIFO memory block that is selected from at least two of a plurality of FIFO memory blocks until the highest priority FIFO memory block is empty. The interface inhibits transfer of data to the data receiving device from remaining ones of the FIFO memory blocks, until the highest priority FIFO memory block is empty. Transmission of data from the highest priority FIFO memory block and inhibited transfer of data from remaining ones of the FIFO memory blocks, take place in response to an indication from the data receiving device that the data receiving device is enabled to receive data from the at least two of the FIFO memory blocks.

Priority encoding for FIFO memory devices that interface multiple ports to a data receiving device

Described is a last stage decoder that generates a local word line signal within a bank of a single-ported memory cell array structure. The decoder inputs predecoded global row address signals, as well as predecoded local row address signals. In order to generate the local word line signal, and thus access a memory cell within a given bank, both one predecoded global row address signal, as well as one predecoded local row address signal must be present. The predecoded local row address signal turns on a pass gate transistor, and allows the predecoded global row address signal to pass through the pass gate transistor and create the local word line signal.

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Lawrenceville, GA, United States of America

Robert H Bishop