Maxeler Technologies Limited

Xilinx, Inc.

Robert Gwilym Dimond

Oliver Pell

James Barry Spooner

Itay Greenspon

Prasanna Sundararajan

David W Bennett

Jeffrey M Mason

Jacob Bower

Lauren B Wenzl

Richard Berry

There is provided a method for processing multiple sets of data concurrently in a statically scheduled pipelined stream processor by allowing a data set to enter the pipeline while another data set is being processed. Dedicated logic units enable independent control of each of the data sets being processed.

Processing data sets using dedicated logic units to prevent data collision in a pipelined stream processor

Embodiments of the invention provide a method of automatically generating a hardware stream processor design including plural processes and interconnect between the plural processes to provide data paths between the plural processes, the method comprising: providing an input designating processes to be performed by the stream processor; automatically optimizing parameters associated with the interconnect between processes within the design so as to minimise hardware requirements whilst providing the required functionality; and generating an optimized design in accordance with the optimization.

Method and apparatus and software code for generating a hardware stream processor design

Disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting nodes in the graph; inserting, on each edge, monitoring hardware to monitor flow of data along the edge. Also disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting the nodes in the graph; inserting, on at least one edge, data-generating hardware arranged to receive data from an upstream node and generate data at known values having the same flow control pattern as the received data for onward transmission to a connected node.

Method of debugging control flow in a stream processor

A method of configuring a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph includes a data path to be implemented in hardware as part of the stream processor, an input, an output, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The data path is partitioned into a plurality of discrete regions, each region operating on a different clock phase and having discrete control logic elements. Phase transition registers to align data separated by a boundary between regions having different clock phases are introduced into the data path at the boundary. The graph and control logic elements define a hardware design for the pipelined parallel stream processor.

Systems and methods for reducing logic switching noise in parallel pipelined hardware

A method of utilizing high level synthesis to automatically configure control logic of a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph includes a data path to be implemented in hardware as part of the stream processor, an input, an output, functional objects, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The functional objects are grouped based upon having a cycle position dependent upon common factors. Common control logic elements are allocated to groups of functional objects. The graph and allocated control logic is used to define a hardware design for the pipelined parallel stream processor.

Systems and methods for optimizing allocation of hardware resources to control logic in parallel pipelined hardware

A method of utilizing high level synthesis to automatically configure control logic of a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph comprises a data path to be implemented in hardware as part of said stream processor, an input, an output, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The data path is partitioned to divide it into a plurality of discrete regions. Discrete control logic elements are assigned to each region using high level synthesis. The graph and assigned control logic is used to define a hardware design for the pipelined parallel stream processor.

Systems and methods for configuration of control logic in parallel pipelined hardware

The invention provides a method of transferring data from a data array within a main memory of a computer to an accelerator for processing, the embodiment of the method comprising: at the accelerator, requesting data from the main memory and generating a data stream between the main memory and the accelerator, the generated data stream including data from the data array; and, using an offset to determine the scheduling of array elements within the generated data stream.

Method of transferring and processing data for efficient parallel computation

Method of transferring data, a method of processing data, an accelerator, a computer system and a computer program

Method of transferring data with offsets

Generation of cache architecture from a high-level language description is described. A description of an application in a high-level programming language is obtained. A data flow representation is generated from the description suitable for providing an implementation in hardware. The generating includes: identifying accesses to memory associated with the description; determining that at least a portion of the accesses to memory do not have one or more data dependencies for locally cacheable data; and assigning the portion to a distributed cache.

Growing community of inventors

London, United Kingdom

Robert Gwilym Dimond