Nxp Usa, Inc.

Freescale Semiconductor,inc.

Robert Greenwood

Paul Herbst

Haku Sato

Robert Bahary

An integrated circuit (IC) package of an electronic device includes a first input coupled to a first voltage rail and a second input coupled to a second voltage rail. The IC package further includes a set of one or more input/output (IO) pad cells and a power sequence detector coupled to the first and second voltage rails. The power sequence detector monitors the first and second voltage rails and configures the set of one or more IO pad cells to operate at one of a non-zero first voltage level or a non-zero second voltage level depending on which of the first voltage rail and the second voltage rail ramps up to a corresponding specified voltage level first.

Configuration of default voltage level for dual-voltage input/output pad cell via voltage rail ramp up timing

A first-in first-out (FIFO) buffer system includes FIFO control logic and first and second storage partitions. Each storage partition includes a corresponding single-port memory bank and a prefetch buffer. The FIFO control logic alternates processing of PUSH commands between the first and second storage partitions. Additionally, the FIFO control logic anticipates POP commands based on the FIFO order and the alternating PUSH arrangement by initiating prefetches of data so that data to be accessed by a POP command is available at either the prefetch buffer (if the prefetch has completed) or the output of the single-port memory bank (if the prefetch has not yet completed) of the corresponding storage partition at the time the POP command is received, thereby enabling the output of the data for the POP command in the same clock cycle in which the POP command is received.

FIFO buffer system providing same clock cycle response to pop commands

A semiconductor device includes a single substrate including circuitry to implement a processor, a memory coupled to the processor, an audio interface module configured to provide data in pulse-code modulation (PCM) format having a first signal to noise ratio (SNR), and a medium quality speaker module configured to receive the PCM data, convert the data from the PCM format to a pulse-width modulation (PWM) format independently of the processor, and provide the data in the PWM format having a second SNR to at least one general purpose input-output pin on the substrate, the first SNR is greater than the second SNR.

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Austin, TX, United States of America

Robert Greenwood