Digital Equipment Corporation

Robert Giggi

Robert E Stewart

John V Levy

Thomas A Northrup

John E Buzynski

An interface circuit (10) for coupling a parallel data device (12) to a serial data channel (14, 16) over which Manchester-type codes are transmitted. In the interface circuit, an efficient and reliable Manchester decoder (22), comprising a flip-flop (50), an exclusive-or gate (52), and at least one delay line (58A or 58B) separates the data and clocking signals. The serial data signals are clocked into a serial register (30) under control of the external clocking signals from the channel. A carrier detector (24) enables the serial register only when valid information signals are present. A parallel data register (40) receives in parallel the data from the serial data register. To get in phase the external clocking signals with the internal clock source, an internal clock synchronizing circuit (34, 42) recycles the internal clock source upon the occurrence of a synchronizing character that is transmitted over the serial data channel. In this fashion, the internal operations of the parallel data transfers are in phase, but isolated from the external clocking signals so that in the event that the external clocking signals become corrupted due to noise or simultaneous transmissions of information signals by different devices, the internal parallel transfer operations may continue freely without disruption.

Interface for serial data communications link

A memory arrangement for a digital data processing system that includes a high-speed associative memory unit and a random access back-up unit. The associative memory unit contains a multiple location address memory and a multiple location data memory wherein there is a correspondence between each address location and a data location. Each time a central processor initiates a reading operation, it issues an address to define a data location. If the associative memory unit contains that address at a location in its address memory, it performs a reading memory cycle and transfers data from the corresponding location in the data memory directly to the central processor. If the data is not available in the associative memory unit during a reading operation, or if the central processor is transferring data to the address location during a writing operation, the associative memory unit causes the back-up unit to perform a corresponding memory cycle. If the address memory in the associative memory unit contains a corresponding address, the new data also is transferred to the corresponding location in the data memory. Secondary memory units, such as disk memory units, and input/output units also communicate with the back-up memory unit and the associative memory unit. For example, a disk memory unit may transfer data to locations in the back-up memory unit, and such a device transmits an address to the back-up memory unit during such transfers. If the associative memory unit contains data from a corresponding location, the contents of the addressed location are modified to indicate that the data in the corresponding back-up location has been changed.

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Peabody, MA, United States of America

Robert Giggi