Sharp Kabushiki Kaisha Corporation

Lattice Semiconductor Corporation

Sharp Microelectronics Technology, Inc.

Sharp Electronics Corporation

Robert Gary Pollachek

Giao N Pham

Michael J Griffus

Sheng Teng Hsu

Fabiano Fontana

Loren McLaury

In one embodiment, an integrated programmable device has a plurality of current sense amplifiers for reading data from non-volatile memory and a reference generator that provides common bias reference voltages to the sense amplifiers. The sense amplifiers can read data from the non-volatile memory at low power supply voltage levels (e.g., 750 mV) relative to the nominal supply level (e.g., 1.2V). Each sense amplifier has a trans-impedance amplifier that converts a memory bit-line current into a voltage level indicative of whether a selected memory cell is programmed or erased. The trans-impedance amplifier has a current mirror with a high-threshold regeneration device that lowers the sense amplifier's range of operating voltages. Each sense amplifier also has a level-shifted inverter that further lowers the sense amplifier's operating voltage range. The reference generator generates a ground-referenced bias voltage that each sense amplifier or group of sense amplifiers converts into a local, supply-referenced bias voltage.

Low-voltage current sense amplifer

Low-voltage current sense amplifier

In one embodiment, a voltage discharge (VD) system has a slow VD subsystem that provides two concurrent discharge current paths to at least begin to discharge both positive and negative voltages: a first path from the positive-voltage node to ground and a second path from the positive-voltage node to the negative-voltage node. In addition to this relatively slow VD subsystem, the VD system can also have a conventional fast VD subsystem that is turned on after the slow VD subsystem has reduced the positive and negative voltages to some degree (e.g., half of each charge removed). Such a VD system can eliminate dangerous overshoot conditions, even when control-signal skew is present.

Voltage discharge circuit having divided discharge current

A low noise CMOS buffer has been provided which includes the advantages of having a stable load impedance and a linear-ramped current waveform at the output. The buffer adds waveform shaping transistors to delay the turn on of the driver circuits, and to shape the voltage and current waveforms of the drivers. These critically placed waveform shaping transistors accomplish the function of turning off the drivers in a manner to encourage an opposite polarity linear ramp current waveform at the buffer output. A method of using waveform shaping transistors to form a stable output impedance and a linear-ramped current waveform at the output of a buffer is also provided.

Constant impedance, low noise CMOS buffer

A method of, and apparatus for, decoupling a defective or otherwise non-operational memory block from the power lines of a memory device is disclosed. Defects which cause excessive current consumption in defective memory blocks can be repaired through this approach. Mass-production yields can be improved significantly.

Method and apparatus for repair of memory by redundancy

A self-aligned multi-level interconnect structure and a method for fabricating the same are disclosed. The multi-level interconnect structure is fabricated by the steps of: (1) forming a first plurality of spaced-apart insulative layers [231-233], where the first plurality includes a top insulative layer [233]; (2) forming a second plurality of spaced-apart conductors [221,222] and positioning them interdigitally between the insulative layers; (3) defining a first hole [233h] extending through the top insulative layer [233]; (4) using the first hole [233h] to define a succession of self-aligned subsequent holes [222h,232h,22ih,231h] through the underlying conductors and insulative layers, each successive hole being continuous with and self-aligned to one above it; and (5) defining a through-conductor [223] extending through the succession of self-aligned holes. The self-aligned multi-level interconnect structure is employed in a multi-layer SRAM cell.

Growing community of inventors

Vancouver, WA, United States of America

Robert Gary Pollachek