Freescale Semiconductor,inc.

Nxp USA, Inc.

Continental Teves, Ag and Company Ohg

Gach, Robert

Robert Gach

Tobias Beckmann

Ireneusz Janiszewski

Claas Cornelius

Didier Salle

Dominique Delbecq

Hao Li

Pierre Turpin

Gilles Montoriol

Hugues Beaulaton

Thierry Cassagnes

Frank Michel

Pierre Pascal Savary

Christophe Landez

Sergey Sergeevich Ryabchenkov

Akbar Ghazinour

Stephane Colomines

Eugeny Alexandrovich Kulkov

A method for transmitting messages in a data bus system, wherein the messages can be transmitted in the form of data frames by a data bus and a data frame that is to be sent by a bus subscriber is checked for a piece of changeover information, which method is furthermore distinguished in that changeover of the rise time and/or edge shape of edges of bit pulses of the data frame that is to be sent is performed on the basis of the presence of a defined value of the piece of changeover information. In addition, a corresponding transceiver and to an electronic control unit is disclosed.

Method for transmitting messages in a data bus system, transceiver and electronic control unit for a motor vehicle

A method for protecting configuration data from a data bus transceiver operable in a subnetwork mode. The configuration data are provided for comparison with data bus message data arriving via a data bus. A reference checksum for the configuration data is generated and stored, and recurrently checked. In the event of an identified alteration, a wake-up signal and/or a piece of error information is output. During or after writing the configuration data to a configuration register via the data bus or directly before the change to the low-power mode of the electronic control unit, a checksum unit forms a checksum that is stored in a reference register. In the low-power mode of the electronic control unit, the checksum for the configuration is repeatedly recomputed and compared with the checksum stored in the reference register. If the recomputed checksum does not match the stored checksum, a wake-up process is triggered.

Method for protecting configuration data from a data bus transceiver, data bus transceiver and data bus system

A CAN FD frame comprises one or more portions provided at a normal bit rate that includes an end-of-frame field consisting of a succession of at least seven recessive bits. A method for detecting the end-of-frame of a CAN FD frame in an input bit stream entails providing a recessive bit count; defining a stretched bit transmission time longer than the bit transmission time associated with the high data rate; stretching the bit transmission time of each dominant bit succeeding a recessive bit in the input bit stream to the stretched bit transmission time to generate a conditioned input bit stream; sampling the conditioned input bit stream at a bit counter rate to generate a sampled bit stream; resetting the recessive bit count in response to each dominant bit in the sampled bit stream; and incrementing the recessive bit count in response to each recessive bit in the sampled bit stream.

CAN FD end-of-frame detector, CAN bit stream processing device, method for detecting the end of a CAN FD frame, and method of operating a CAN bit stream processor

A network receiver for a network using distributed clock synchronization and a method of adjusting a frequency of an internal clock of the network receiver are provided. The network receiver receives from the network an input signal and has an internal clock for generating a clock signal. The network receiver further includes a clock bit comparator and an adjustment signal generator. The clock bit comparator compares lengths of a first time period lapsed while receiving at least five consecutive bits of the signal and of an internal clock time interval representing the same number of bits as a number of bits of the first time period. The adjustment signal generator generates a frequency adjustment signal for controlling a frequency of the internal clock in dependence of a result of the comparison of the lengths to reduce a difference between the lengths.

Network receiver for a network using distributed clock synchronization and a method of adjusting a frequency of an internal clock of the network receiver

A direct-sequence spread spectrum signal receiving device may comprise a receiver unit, a chip sequence generating unit, a correlation unit, and comparison unit. The receiver unit may extract a chip stream from a radio-frequency signal, said chip stream containing a first chip sequence. The chip sequence generating unit may generate a plurality of trial chip sequences on the basis of a first trial chip sequence and on the basis of a plurality of index rotations. The correlation unit may determine a plurality of correlation values on the basis of said plurality of trial chip sequences and on the basis of said first chip sequence, each of said correlation values indicating a degree of correlation between a respective one of said trial chip sequences and said first chip sequence. The comparison unit may determine whether a maximum one of said correlation values exceeds a defined threshold value.

Direct sequence spread spectrum signal receiving device and method

An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.

Integrated circuit comprising frequency generation circuitry for controlling a frequency source

Growing community of inventors

Seysses, France

Robert Gach