Stmicroelectronics Gmbh

Sgs-thomson Microelectronics Limited

Stmicroelectronics (research & Development) Limited

Stmicroelectronics S.r.l.

Robert G Warren

Robert M Mills

David Martin Smith

A method of encoding data and timing information on a single line comprising: asserting a first edge on the single line to encode said timing information; asserting a second edge on the single line a selectable time period after said first edge, said selectable time period representing said data, characterized in that: said step of asserting said first edge comprises supplying a clock signal to a clock input of a flip-flop; and the step of asserting the second edge comprises supplying the output of the flip-flop to an input of a programmable delay line having a data input connected to receive said data and an output connected to a reset input of the flip-flop, whereby an output of the flip-flop provides said encoded data and timing information on the single line.

Pulsed serial link transmitting data and timing information on a single line

An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Tap time division multiplexing with scan test

Apparatus for transmitting a clock and data from a first module to a second module connected by a single outward line and a single return line, comprising: means for transmitting a data pulse on the single outward line comprising means for asserting a first edge on said single outward line, said first edge representing a timing edge for the clock and means for asserting a second edge on the single outward line a selectable time period after said first edge, said selectable time period representing said data; and means for receiving a return pulse on said single return path comprising means for receiving a first edge and a second edge on the single return line, the first and second edges being separated by a first time period, said first time period representing an acknowledgement.

Flow controlled pulsed serial link

Circuitry for decoding data from a pulsed signal received on a single line, the circuitry comprising receiving means for receiving a first edge and a second edge on the single line, the first and second edges being separated by a time period, the time period representing said data; decode circuitry comprising determining means arranged to determine a value of the time period and decoding means arranged to decode said data based on said determined value of the time period; a memory arranged to store a reference value; and calibration means for calibrating said decode circuitry based on a comparison between said determined value of the time period and said reference value, wherein the determining means comprises a plurality of sampling units for sampling said pulsed signal at different times, and selection means for selecting the output of one of said sampling units to decoded.

Calibrated pulsed serial link

An integrated circuit comprising: at least one test input for receiving test data; test control circuitry between the at least one test input and circuitry to be tested; wherein the test data is clocked in on a rising clock edge and a falling clock edge.

TAP sampling at double rate

A method of delaying successive first and second input signals by first and second different selectable time periods using a programmable delay line comprising a sequence of delay elements, each introducing a delay, the method comprising the steps of: providing a control signal to each delay element, the control signal selectively being in a first logic state or a second logic state wherein in a first logic state the delay element selects an input from an adjacent delay element thereby to select the delay elements as part of a set of delay elements introducing said selectable time period and in a second logic state the delay element is not selected in the set; setting the control signals for a first number of adjacent delay elements to the first logic state to introduce the first selectable time period wherein the control signals for the delay elements in the sequence not in the first number are set to the second logic state; and setting the control signals of a second number of adjacent delay elements to the first logic state to introduce a second selectable time period, wherein the control signals for the delay elements in the sequence not in the second number are set to the second logic state; whereby the reconfiguration time between the first and second input signals is less than the maximum delay introduced by the sequence of delay elements.

Programmable digital delay

Circuitry for synchronizing communications between clock environments wherein a change of state is transmitted from a first clock environment to a second clock environment, the first clock environment being timed by a first clock signal and the second clock environment being timed by a second clock signal, the first and second clock signals having nominally the same frequency but an unknown phase relationship, the circuitry comprising: delay means in the first clock environment arranged to generate a plurality of timing signals by delaying said first clock signal by respectively different delay values; sampling means in the second clock environment for sampling said plurality of timing signals at timing determined by said second clock signal thereby generating a plurality of sampled timing signals; and determining means for generating a control signal based on said plurality of sampled timing signals and outputting said control signal for controlling the transfer time of said change of state.

Isochronous synchronizer

TAP time division multiplexing with scan test

A routing block using a switch with a pulsed serial link. An input of a routing block is supplied with an information signal. The routing block has multiple outputs. The information signal includes a first edge and a second edge on a single line. The first and second edges are separated by a time period. One of the first and second edges represents information conveyed by the signal. The other one of the first and second edges provides timing information. The information signal controls the routing block to select one of the multiple outputs and the transferring the signal to said selected one of said multiple outputs. Depending on the number of bits of information transmitted in each pulse and the number of switches controlled by the control information, the decoded control data will include at least one bit outputted serially to a control signal generator block.

Pulse link and apparatus for transmitting data and timing information on a single line

Tap sampling at double rate

A system for controlling communications between a host and a target, the system having a data input for receiving a data signal, a clock input for receiving a clock signal, an oversampling circuit for sampling a received data signal and generating a control signal to control processing of the received data signal based at least in part on samples of the received data signal.

System and method for connecting a host and a target

An integrated circuit comprising: a plurality of portions, each portion including test control circuitry; at least one test input arranged to receive test signals; and a multiplexer between the at least one test input and the test control circuitry, the multiplexer having a least one control input whereby the multiplexer is controllable to direct test signals to one of the plurality of portions.

Tap multiplexer

An integrated circuit including functional circuitry; test circuitry connected to the functional circuitry, wherein the test circuitry is arranged to control the testing of the functional circuitry; and clock signal generating circuitry connected to both the functional circuitry and the test circuitry. The test circuitry is arranged to use the clock signal for testing the functional circuitry.

Method and apparatus for testing a functional circuit at speed

An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a soft reset signal for resetting the second circuitry, the integrated circuit further including: a soft reset hold circuit clocked in the first clock environment connected to receive the soft reset signal and to generate an output reset signal in an asserted state; and a synchronizer clocked in the second clock environment connected to receive the output reset signal and to generate a retimed reset signal in an asserted state after a predetermined period, wherein the retimed reset signal is fed back to the soft reset hold circuit to cause the output reset signal to adopt a deasserted state at the end of said predetermined period.

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Bristol, United Kingdom

Robert G Warren