Sequence Design, Inc.

Frequency Technology, Inc.

Robert G Mathews

Keh-Jeng Chang

Li-Fu Chang

Shih-Tsun Alexander Chou

Wei Ey Li

Donald Vick Organ

Douglas Kaufman

Japinder Singh

Martin G Walker

Hazem Almusa

Vinay Srinivas

Larry Ke

Abhay Dubey

Shih-tsun A Chou

Xu Yang

A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, 'hot spots' in the physical design are identified for local transformation using a 'bidirectional combinational total negative slack' (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.

Method and apparatus for interconnect-driven optimization of integrated circuit design

A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library. Using this parasitic extraction system, parasitic impedances, including inductance, may be extracted for an integrated circuit layout, thus allowing more accurate modeling and timing analysis of the integrated circuit layout to be obtained.

Method and system for extraction of parasitic interconnect impedance including inductance

A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, &ldquo;hot spots&rdquo; in the physical design are identified for local transformation using a &ldquo;bidirectional combinational total negative slack&rdquo; (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.

A method measures a resistance in a test structure to determine the sheet resistivity of a test structure. In one embodiment, a family of test structures is provided to determine the effective sheet resistivity of a conductor as a function of its width. The method is applicable to conductors in manufacturing processes in which &ldquo;slots&rdquo; or &ldquo;islands&rdquo; are created in the conductor to prevent dishing during chemical-mechanical polishing.

Method for determining on-chip sheet resistivity

A method provides estimations of physical interconnect process parameter values in a process for manufacturing integrated circuits. The method includes fabricating test structures each providing a value of a measurable quantity corresponding to a value within a range of values of the physical interconnect process parameters. In some embodiments, the measured value is used to derive the values of the physical interconnect process parameters, either by a numerical method using a field solver, or by a closed-form solution. The values of physical interconnect process parameters involving physical dimensions are also obtained by measuring photomicrographs obtained using a scanning electron microscope from cross sections of test structures. In some embodiments, a family of test structures corresponding to a range of conductor widths and a range of spacings between conductors are measured.

Methods for determining on-chip interconnect process parameters

A method models conductive regions of a semiconductor substrate in conjunction with conductors in the interconnect structures above the semiconductor substrate. Such a method allows highly accurate extraction of capacitance in planar (e.g., shallow trench isolation) and non-planar (e.g., thermal oxide isolation) semiconductor structures. This method is particularly applicable to modeling dummy diffusion regions prevalent in shallow trench isolation structures. An area-perimeter approach simplifies calculation of capacitance without using a 3-dimensional electric field solver. A method is also provided for extracting a capacitance associate with a contact, or a connecting conductor between two conductor layers.

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Los Altos, CA, United States of America

Robert G Mathews