Texas Instruments Corporation

Sandisk Technologies Inc.

Robert G Gugel

Gary Lin

Umang Thakkar

Merril Ray Newman

Burke S Henehan

The various implementations described herein include systems, methods and/or devices for reading data stored in a storage device. In one aspect, read commands are executed, each command for reading a requested logical group of data from a specified logical address comprising one or more logical portions. A first physical location in the storage device corresponding to the logical address is identified from a mapping table, and data is read. In accordance with a determination that the first physical location stores less than all of the logical group of data, a second physical location is identified based on information contained within the data from the first physical location, and data is read from the second physical location. Data read from the one or more physical locations is decoded to produce the requested logical group of data, which is then returned.

Reading logical groups of data from physical locations in memory using headers

The various implementations described herein include systems, methods and/or devices for storing data in a storage device. In one aspect, commands are executed, each command for storing in a storage device a logical group of data comprising one or more logical portions and having a logical address. For each command, in accordance with a determination that a remaining capacity of a first physical memory portion is less than a threshold capacity, data is stored for a head logical portion in a first physical location corresponding to the first physical memory portion. Furthermore, data is stored for a tail logical portion in a second physical location corresponding to a second physical memory portion. Mapping entries are stored in a mapping table, where the mapping entries map the corresponding logical address to at least the first physical location in the storage device.

Writing logical groups of data to physical locations in memory using headers

According to one embodiment of the present invention, a system ( ) for data transfer is disclosed that comprises a transfer memory ( ) having one or more buffers ( , and ). Accessing units comprising direct memory access units ( and ) are coupled to the transfer memory ( ) and are operable to access the transfer memory ( ). Pointers ( , and ) stored in the transfer memory ( ) direct the accessing units ( and ) to selected ones of the buffers ( , and ) such that no two accessing units ( and ) are simultaneously accessing one buffer ( , and ). More specifically, the pointers ( , and ) may also direct a memory control unit ( ) to a buffer that is not being accessed by an accessing units ( and ). According to one embodiment of the present invention, a method for data transfer is disclosed. First, a transfer memory ( ) comprising one or more buffers ( , and ) is provided. Second, pointers ( , and ) indicating selected ones of the buffers are stored in transfer memory ( ). Finally, accessing units comprising direct memory access units ( and ) operable to access the transfer memory ( ) are directed to the buffer indicated by the pointer ( and ), such that no two accessing units ( and ) are simultaneously accessing one buffer ( , and ). More specifically, a transfer memory control unit ( ) may be directed to a next buffer that is not being accessed by an accessing unit ( and ).

Method and system for data transfer

An IEEE 1394 serial bus ( ) is interfaced utilizing a physical layer ( ) to extract the data and a link/transaction layer controller ( ) to interface the data from the physical layer ( ) to a host system. The host system consists of a peripheral device ( ) which is interfaced with various host buses ( ). The link/transaction layer controller ( ) is operable to emulate the microcontroller function such that addresses can be transmitted to the peripheral device ( ) along with data, such that a remote node can access the peripheral device ( ) by transmitting address and data information thereto. Alternatively, address and data information can be transmitted from the peripheral device ( ) to the controller ( ) which will process the received address and data and transmit it to a remote node.

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Garland, TX, United States of America

Robert G Gugel