Data General Corporation

Robert G Gelinas

James Marriot Guyer

William F Baxter

David L Keating

Rob P Valentine

Pat J Weiler

Doug J Tucker

Art A Sherman

Liz M Truebenbach

Phil J Roux

Barry E Gillott

Jeff S Kimmell

Rob J Pike

Simon N Yeung

Michael F Hunt

Andrea Heyda

Tom V Radogna

Joseph Cox

Dan R Huck

Michael Sporer

Micheal Sporer

Thomas V Radogna

High availability computer system and methods related thereto

A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency. The motherboard also includes GTL backpanel interface logic, system clock generation and distribution logic, and local resources including a micro-controller for system initialization. A crossbar switch connects the various logic blocks together. A fully loaded motherboard contains 2 JP daughterboards, two PCI expansion boards, and up to 512 MB of main memory. Each daughterboard contains two 50 MHz Motorola 88110 JP complexes, having an associated 88410 cache controller and 1 MB Level 2 Cache. A single 16 MB third level write-through cache is also provided and is controlled by a third level cache controller.

Bus arbitration system for multiprocessor architecture

Symmetric multiprocessing computer with non-uniform memory access

A system for use in a floating point computation unit for providing a sign/magniture subtraction operation, which system uses propagate/generate logic responsive to the subtraction operands to produce intermediate and final propagate and generate outputs. First carry computation logic is responsive to the final propagate and generate outputs and to a carry-in bit to produce final carry outputs and a carry-out bit. The latter outputs are used to produce a first subtraction result. Second carry computation logic responds to the intermediate propagate and generate outputs to produce second final carry outputs. The latter outputs and selected intermediate propagate outputs are used to produce a second subtraction result. The carry-out bit then selects one of the two subtraction results as the final subtraction result.

Technique for providing a sign/magnitude subtraction operation in a

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Westboro, MA, United States of America

Robert G Gelinas