Ncr Corporation

Genrad, Inc.

Other

Robert G Fulks

Robert E Enfield

Robert J Hager

Stanley E Rose

Eric Sacher

Edward H Greenwood

Robert E Anderson

A tester (10) for testing an electronic circuit (22) has test terminals (18a-d) that are to be connected to the terminals (20a-d) of the circuit under test. The tester terminals (18a-d) are placed in the states required for testing by formatter circuits (32a-d) in accordance with state codes generated by state-code generators (24a-d). However, the state-code generators (24a-d) are not required to generate every code as quickly as those codes are needed by the formatters (32a-d), because first-in, first-out memory stacks (30a-d) are interposed between the state-code generators (24a-d) and the formatters (32a-d). This permits the state-code generators (24a-d) to employ relatively slow--and thus relatively inexpensive--memories (26).

Circuit tester

Apparatus and method for the monitoring of the manipulation of the keys of an instrument comprises monitoring apparatus which takes the form of a pressure sensing device, associated with each key, that can be fabricated in a configuration compatible with the instrument. According to one embodiment, the pressure sensing devices can be arranged so that the monitoring apparatus can be positioned on a balance rail of a piano keyboard. In this embodiment, the monitoring configuration can be fabricated and conveniently retrofitted to a standard keyboard. The pressure sensing device comprises a resistive element, a conducting element, and a force transducer ink layer separating the resistive and conducting elements. The resistance of the resistive element is monitored and when pressure is applied to the pressure sensing device, a change in resistance can be measured. Because the resistance is a function of pressure, the amount of pressure used to activate the key can be determined.

Method and apparatus for sensing activity for a keyboard and the like

A high speed print head system includes a print head pivotally and resiliently coupled to a frame which is laterally movable on a carriage system. The print head includes an elongated nose piece having therein a plurality of print rods which can be controllably forced beyond the end of the nose piece to impact a ribbon and paper supported by a platen to produce dots on the paper. The pivotal and resilient coupling is achieved by means of a flexure having first and second opposed connection points connected to the frame and third and fourth opposed connection points connected to the print head. Two permanent magnets are rigidly attached to the frame substantially above the axis of the elongated nose piece and substantially symmetrically with respect to the elongated nose piece. A pair of electromagnets rigidly attached to the print head opposite the respective permanent magnets are controllably energized to produce continuously variable forces between the frame and the print head. The continuously variable forces produce continuously variable pivoting of the print head about its neutral position, whereby high resolution character printing can be effected with a minimum dot overlap, and consequently with a minimum number of dot printing operations.

High speed print head system and method

A portable processor-oriented digital tester and method for isolating faults in digital printed circuit boards under test. The digital tester includes a processor, a main memory and a plurality of driver/sensor circuits. The main memory stores a signature file containing known correct signatures for the nodes of a board under test and also stores an image file which contains information defining the topology of the board under test. The driver/sensor circuits are programmable to receive test information generated by a test program stored in the main memory, transmit such information to inputs of a board under test, and receive information produced by the board under test in response to the input test information. The response received from outputs of the board under test is compared to a corresponding known-correct response to identify a faulty output of the board under test. The processor refers to the image file to identify a logic element driving the faulty output and to identify the nodes which are inputs to the logic element. The processor causes instructions to be displayed to the operator of the portable digital tester to instruct the operator to probe the input nodes of the logic element. A signature is generated for each node and compared to a corresponding known correct signature for that node as it is probed by the operator to identify a faulty input node. For each faulty node found, the measured signature, the initial state, and a number equal to the smaller of an input test number of the known correct initial transition of the faulty node and an input test number of the first incorrect transition of the faulty node is stored in a history file having pointers to the image file for each node. If a component is found having a faulty output and all good inputs, that component is identified as defective. If a loop is identified by the main processor, the operator is instructed to test all external inputs to the loop; if a faulty external input is found, the loop is resolved, and the processor instructs the operator to probe another node. If the external inputs are all good, the main processor scans the history table to determine which node in the loop failed first and indicates that the component driving that node is the probable fault.

Method and apparatus for isolating faults in a logic circuit

Portable tester and method for testing a variety of circuit boards without utilizing adaptor boards for re-routing input test signals and supply voltage from the tester to pins of the board under test. A plurality of edge adaptors having different pin spacings have their respective pins connected in parallel to corresponding edge connector stake pins. Each edge connector stake pin is connected to or isolated from the corresponding driver/sensor stake pin by means of a switch. Each driver/sensor stake pin is connected to the input/output terminal of a programmable driver/sensor circuit. A plurality of power supply stake pins are connected to various power supplies of the portable tester. Connectors coupled to the family board can be utilized to route power supply voltages to electrically isolated edge connector stake pins. Isolated driver/sensor outputs can be routed to other edge connector stake pins. A main processor stores a test program and transmits data and control information to predetermined driver/sensor circuits. A high speed processor is coupled between the main processor and the inputs of the driver/sensor circuits. The high speed processor memory can store a bus-defining subroutine containing a sequence of data shifting instructions which shift a word in the shift register to the input of specified driver/sensor circuits at high speed. The high speed processor can synchronize the operation of the portable tester with an asynchronously operating printed circuit board under test.

Method and apparatus for transmitting data to a predefined destination

Portable tester and method for testing a variety of printed circuit boards without utilizing specialized adaptor boards for rerouting input test signals and supply voltages from the tester to various pins of the board under test. A plurality of edge connectors have their respective pins connected to corresponding edge connector stake pins. Each edge connector stake pin is connected to or isolated from the corresponding driver/sensor stake pin by means of a switch. Each driver/sensor stake pin is connected to the input/output terminal of a programmable driver/sensor circuit. A main processor is utilized to store a test program and to transmit data and control information to predetermined driver/sensor circuits. A high speed processor coupled between the main processor and the inputs of the driver/sensor circuits includes a parallel-loadable shift register, an instruction register, an instruction decoder and control circuitry connected to the inputs of the driver/sensor circuitry. The high speed processor memory can store a bus-defining subroutine containing a sequence of data shifting instructions which shift a word in the shift register to the input of driver/sensor circuits specified by the arguments of the shifting instruction at high speed, thereby achieving high speed routing of data from the main processor to the board under test with very few instructions of the test program. Each driver/sensor circuit has programmable pull-up and pull-down termination devices which obviate the need for certain termination resistors on the board under test.

Growing community of inventors

Phoenix, AZ, United States of America

Robert G Fulks