Intel Corporation

Robert Frickey

Xin Guo

Yogesh B Wakchaure

Ning Wu

Kristopher H Gaewsky

Hanmant Pramod Belgal

Iwen Chao

Pranav Kalavade

Paul D Ruby

David J Pelster

Ramkarthik Ganesan

Joseph F Doller

Justin R Dayacap

Technology for an apparatus is described. The apparatus can include a first non-volatile memory, a second non-volatile memory to have a write access time faster than the first non-volatile memory, and a memory controller. The memory controller can be configured to detect corrupted data in a selected data region in the first non-volatile memory. The selected data region can be associated with an increased risk of data corruption after data is written from the second non-volatile memory to the first non-volatile memory. Uncorrupted data in the second non-volatile memory that corresponds to the corrupted data in the first non-volatile memory can be identified. Data recovery in the first non-volatile memory can be performed by replacing the corrupted data in the first non-volatile memory with uncorrupted data from the second non-volatile memory.

Data recovery in memory devices

An apparatus is described. The apparatus includes a storage device having multiple non volatile memory chips and controller circuitry. The controller circuitry is to implement wear leveling of storage cells of the non volatile memory chips at a granularity of segments of storage cell arrays of the non volatile memory chips that share a same disturber node and that are coupled to a same storage cell array wire to diminish disturb errors.

Word line read disturb error reduction through fine grained access counter mechanism

According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.

Configuration information backup in memory systems

Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.

Method and apparatus for reducing read latency for a block erasable non-volatile memory

Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of corrected data. A program command may then be sent with a second page of data and the page of corrected data, to program a page of memory to store the second page of data.

Error corrected pre-read for upper page write in a multi-level cell memory

An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.

Lower page read for multi-level cell memory

Data management logic allocates a portion such as a single plane of a respective multi-plane non-volatile memory device to store parity information for corresponding data striped across multiple planes of multiple non-volatile memory devices. According to one configuration, the data management logic as discussed herein generates parity data based on (a data stripe of) non-parity data stored in multiple planes of multiple different memory devices. The data management logic stores the parity data in the storage plane allocated to store the parity information. Additional configurations include: reserving a parity block amongst multiple non-parity data blocks to store parity data and reserving a parity page amongst multiple non-parity data pages to store parity data.

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Sacramento, CA, United States of America

Robert Frickey