International Business Machines Corporation

Robert Francis Lusch

Howard Thomas Olnowich

John David Jabusch

James William Feeney

Michael Anthony Maniguet

Michael Hans Fisher

Michael W Dotson

Peter Anthony Franaszek

Christos J Georgiou

Joseph M Mosley

George William Wilhelm, Jr

Kevin R Qualters

Terry Leo Sobotta

William S Ebert

John E Swenson

Omar A Saiyid

Jeffrey J Dulzo

An apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. The apparatus is relatively easy to implement and inexpensive to build. The communication media is switch-based and is fully parallel, supporting nodes interconnected by the switching network.

Apparatus for coupling a bus-based architecture to a switch network

An interface includes an enclosure having a plurality of walls interconnected to form a parallelepiped having a space therein. The enclosure is positionable to occupy a plurality of slots located in a computer housing of a first type computer. The enclosure has a width corresponding essentially to a total width of the plurality of slots. The interface further includes a computer subsystem of a second type computer disposed within the space of the enclosure. The computer subsystem includes a circuit card, and a distribution card attached to, and electrically coupled with, the circuit card. The distribution card is connectable to a backplane of the first type computer located external to the enclosure and within the computer housing.

Computer interface for integrating a first computer into a second computer

A new asynchronous approach used to quickly and dynamically switch input port connections to output port connections and to resolve contention. The switch is self-routing in two cycle times at the same high speed serial rate that data is transferred through the switch. The normal mode of the switch requires absolutely no synchronization amongst any of the input and output ports which interface to the switch. The switch is void of centrally controlled clocking and any data buffering. Data traverses the switch only encountering three gate delays&mdash;on-chip receiver, mux, and off-chip driver. Contention is detected and resolved on chip, and yet the logic implementation is extremely simple and low in gate count, so the switch design is never gate limited. The protocol requires several parallel data lines plus two or three control lines.

All-node switch-an unclocked, unbuffered, asynchronous switching apparatus

A method and apparatus for reducing the software overhead of message passing in parallel systems. Special purpose hardware assists in constructing each data message sent through a network. Message passing systems generally require that every message be prefixed with a message header describing the key control parameters of the message. The software task is to construct the message header for every message individually and to transmit the header prefixed to every message. The software is relieved of constructing the message header and uses special purpose hardware to accomplish the job more efficiently.

Automatic hardware message header generator

A method and hardware apparatus provide a fault tolerant and flexible multi-stage network addressing scheme for transmitting a message with a header containing control bits for selecting from various destination checking functions to be performed. Upon arrival of the message at a node, destination checking is performed or not in response to the massage's header. If destination checking is not performed, or if destination checking is performed and indicates that the node is the desired destination for the message, the message is accepted. If destination checking is performed and indicates that the node is not the desired destination for the message, the message is rejected. Destination checking is disabled during address assignment, broadcasting and multi-casting, and replaced with one's complement-based verification of the sending node.

Selectable checking of message destinations in a switched parallel

A conversion apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel (IBM Trademark) bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. A conversion apparatus controls the transfer of data messages from one nodal element across a switch network to another nodal element by using direct memory access capabilities controlled by intelligent bus masters. This approach does not require interactive support from the processor at either nodal element during the message transmission, and frees up both processors to perform other tasks. The communication media is switch-based and is fully parallel, supporting n transmissions simultaneously, where n is the number of nodes interconnected by the switching network.

Apparatus for adapting message protocols for a switch network and a bus

An electronic switching and data transmission system for interconnecting a plurality of buses. A switching network interconnects several multi-drop buses using adapters to connect the buses to the switching network. The adapters implements hardware functions to appear to software as if all devices on the several buses were attached to a single large bus. The system permits higher speed transfer modes by eliminating multi-drop bus limitations.

Switch network extension of bus architecture

A modularly expandable switch-based planar apparatus for insertable multiple bus-based processor cards and/or expansion cards and interconnecting the cards via a multi-stage switch network which resides on the planar apparatus. The cards require no modification or change of any kind, since the connection to the planar apparatus is made as if the planar apparatus contained the standard MicroChannel interconnection. The planar apparatus implements bus converter units to convert the standard bus interface provided by the cards to the switch network interface, so that functions provided by the cards can communicate in parallel over the switch network.

Switch-based microchannel planar apparatus

A broadcast/switching apparatus makes input port to output port connections on a requested basis quickly and dynamically in a standard mode from any one of the input ports to any one of the output ports, in a multi-cast mode from any one of the input ports to a fixed number of subsets of multiple output ports simultaneously, or in a broadcast mode from any one of the input ports to all output ports simultaneously, using a new asynchronous approach to resolve either broadcast or multi-cast contention among input ports. The normal mode of the broadcast/switch apparatus requires absolutely no synchronization among any of the input and output ports which interface to the apparatus. The broadcast/switch apparatus also incorporates a new accept protocol that enables a positive feedback indication to be returned to the sender of a multi-cast or broadcast operation to inform it that the multi-cast or broadcast transmission was correctly received by all elements involved in the multi-cast or broadcast. The broadcast/switch is completely void of centrally controlled clocking and data buffering. Data which traverses the switch encounters only three gate delays--on-chip receiver, mux, and off-chip driver. Contention is detected and resolved on chip. Each broadcast/switch port interface requires several parallel data lines plus four control lines.

Broadcast/switching apparatus for executing broadcast/multi-cast

Disclosed is multi-media switching apparatus for performing digital, analog, and/or optical communications amongst multiple nodes over switching networks. The key aspect of the present invention is the full parallel aspect of the switching apparatus which supports n simultaneously, low-latency connections, where n is the number of functional elements interconnected by the switching network. Any of the n simultaneous transmissions can be digital, analog, or optical in any proportion. In addition, the present invention can also serve as a high-speed distributed controller for the purpose of of selecting analog or optical switches for information transfer between elements of the system.

Multi-media analog/digital/optical switching apparatus

At least-recently used (LRU) storage means and its associated logic maintain usage history for associativity class entries of a cache directory. The storage means includes an independent storage array for each of the bit positions of an LRU binary code pattern. Parity bits are provided in the arrays for each LRU bit. Separate read/write controls simultaneously write updated LRU bits to some of the arrays and read out unchanged LRU bits from the remaining arrays during updating of a usage history entry when its associativity class is used. Pattern checking logic collects the update bits and the unchanged bits during the update cycle to determine whether or not the new entry is a valid LRU combination. A parity bit is written with each of the update LRU bits written into the arrays and parity bits are read out from the arrays with the unchanged LRU bits for parity checking of each unchanged LRU bit during updating of usage history entries.

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Vestal, NY, United States of America

Robert Francis Lusch