Maxim Integrated Products, Inc.

Robert F Scheer

Alexander Kalnitsky

Fanling Hsu Yang

Sang Hoon Park

Michael Rowlandson

Geoffrey C Stutzin

Dmitri A Choutov

Ken Liao

Joseph P Ellul

Ralph N Wall

Tadanori Yamaguchi

Viktor Zekeriya

Jonathan Herman

Glenn Nobinger

Alexei Shatalov

Thomas W Dobson

Joseph Paul Elull

Alexel Shatalov

A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x&#x3e;y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process. As such, the second epitaxy layer has the highest concentration of Ge near the interface of the first and second epitaxy layer. The concentration of Ge is gradually reduced to near 0% at the top surface of the second epitaxy region.

Self-aligned NPN transistor with raised extrinsic base

The present invention provides a method of forming a super self-aligned bipolar transistor with enhanced electrical characteristics. The power gain and frequency response of the transistor are improved by horizontally etching an area for the base region that is wider than the active emitter and collector regions. By removing polysilicon layers within the device, the base region resistance goes down and unwanted capacitive effects are reduced.

Method of forming a super self-aligned hetero-junction bipolar transistor

A method for forming multiple resistors on a substrate. The method initially includes providing a first resistor on the substrate. A first dielectric layer is deposited, patterned, and selectively etched over the first resistor. Second resistor material is provided over the first dielectric layer. Furthermore, landing pad material is provided over the second resistor material. The landing pad material and the second resistor material are then selectively etched. The selective etching forms contacts for the first resistor in a first region, and forms a second resistor and associated contacts in a second region.

Integrating multiple thin film resistors

A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process. As such, the second epitaxy layer has the highest concentration of Ge near the interface of the first and second epitaxy layer. The concentration of Ge is gradually reduced to near 0% at the top surface of the second epitaxy region.

Method of forming self-aligned NPN transistor with raised extrinsic base

A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has an emitter region characterized by a y-shaped structure formed from bilayer polysilicon. The bilayer polysilicon includes a first polysilicon emitter structure and a second polysilicon emitter structure. The method of forming the bipolar transistor includes forming an emitter stack on a substrate. The emitter stack comprises the first polysilicon emitter structure and a plug structure. The emitter stack defines the substrate into a masked portion and exposed adjacent portions. The exposed adjacent portions are selectively doped with a dopant to define an extrinsic base region, wherein the dopant is blocked from entering the masked portion. After selectively doping the extrinsic base region, the plug structure is removed from the emitter stack and the second polysilicon emitter structure is formed on the first polysilicon emitter structure to define the emitter region of the bipolar transistor.

Method of forming self-aligned bipolar transistor

A method of forming a semiconductor device with an inductor and/or high speed interconnect. The method comprises forming an epitaxial layer over the substrate, forming an opening through the epitaxial layer to expose an underlying region of the substrate, forming a first dielectric material within the opening of the epitaxial layer, planarizing the first dielectric layer, forming a second dielectric material layer over the first dielectric material layer, and then forming a metallized inductor over the second dielectric material layer above the opening of the epitaxial layer. In this case, since the inductor and the high speed interconnect do not overlie the conductive epitaxial layer, the degradation in the Q-factor of the inductor, loss characteristics of the high speed interconnect, and 'cross-talk' between conductors are substantially reduced. The resulting semiconductor device is also disclosed.

Method of forming an integrated inductor and high speed interconnect in a planarized process with shallow trench isolation

A method of forming an NPN semiconductor device includes the steps of forming a collector region within a substrate, forming a base region over the collector region, and forming an oxide-nitride-oxide stack over the base region. Once these three structures are formed, an opening is created through the oxide-nitride-oxide stack to expose the top surface of the base region. Then, a doped polysilicon material is used to fill the opening and make electrical contact to the base region. The use of the oxide-nitride-oxide stack with appropriate etching of the opening eliminates the exposure of the base region to reactive ion etch environment typical of prior art methods for forming NPN semiconductor devices. As an option, after the opening of the oxide-nitride-oxide stack is formed, a local oxidation of silicon (LOCOS) and etched can be preformed to create oxide spacers to line the opening wall above the base region.

Method of forming an NPN device

A method for manufacturing an integrated circuit structure is disclosed. The method includes providing a layer of porous silicon, and epitaxially growing a high resistivity layer on the layer of porous silicon. Devices are then formed on the high resistivity layer to produce the integrated circuit structure. The integrated circuit structure is attached to a silica substrate, such that the silica substrate is coupled to the devices. Further, surface contacts are provided on the structure. The layer of porous silicon is then removed.

Method of forming an integrated circuit on a low loss substrate

A new and improved method of forming a thin film resistor is provided herein that overcomes many of the drawbacks of prior art methods. More specifically, the new method of forming a thin film provides for a well-controlled dielectric thickness under the thin film resistor which is useful for laser trimming purpose. The preferred thickness of the dielectric layer is an integer of a quarter wavelength of the optical energy used to laser trim the resistor. The new method also provides contacts to the thin film resistor that do not directly contact the thin film resistor so as to prevent any adverse process effects to the thin film resistor. More specifically, the method of forming a thin film resistor includes the steps of forming a pair of spaced-apart polysilicon islands over a semiconductor substrate, forming a dielectric layer over and between the polysilicon islands, forming contact holes through the dielectric layer to expose respective first regions of the polysilicon islands, forming a layer of thin film resistive material that extends between respective first regions of the polysilicon islands, forming another dielectric layer over the polysilicon islands and over the thin film resistive material layer, and forming metal contacts through the second dielectric layer in a manner that they make contact to respective second regions of the polysilicon islands, wherein the first and second regions of the polysilicon islands are different.

Method of forming laser trimmable thin-film resistors in a fully planarized integrated circuit technology

A method of forming a shallow-deep trench isolation (SDTI) is provided that includes the steps of forming a pair of deep trenches through a silicon on insulator (SOI) layer without substantially disturbing an underlying buried oxide (BOX) layer. Once the deep trenches are formed, the trenches are filed with suitable electrical isolating materials, such as undoped poly-silicon or dielectric material, and etched back to obtain a substantially planarized top surface. Subsequently, an active nitride layer is deposited on the planarized top surface, and then a pair of shallow trenches are formed. The shallow trenches are formed using a low selectivity etch to uniformly etch a deep trench liner oxide, the SOI layer and the electrical isolating material which have interfaces at non-perpendicular angles with respect to the direction of the etching. Once the shallow and deep trenches are formed, subsequent processing including filling the shallow trench, annealing and chemical-mechanical polishing can be performed.

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Portland, OR, United States of America

Robert F Scheer