Adv Antest Corporation

Robert F Sauer

Anthony Le

Hiroaki Yamoto

Niels Markert

Rochit Rajsuman

Hiroki Yamoto

Shigeru Sugamori

Ankan Pramanick

Mark Elston

James Alan Turnquist

Leon Chen

Bruce R Parnas

Jun Makino

Kiyoshi Fukushima

A distributed operating system for a semiconductor test system, such as automated test equipment (ATE), is described. The operating system includes a host operating system for enabling control of one or more site controllers by a system controller. One or more local operating systems, each associated with a site controller, enable control of one or more test modules by an associated site controller. Each test module performs testing on a corresponding device-under-test at a test site.

Method and apparatus for testing integrated circuits

An event based test system for testing an IC device under test (DUT) designed under an automatic electronic design (EDA) environment. The event based test system includes an event memory for storing event data derived directly from simulation of design data for an intended IC in the EDA environment where the event data to denote each event is formed with time index indicating a time length from a predetermined point and an event type indicating a type of change at an event, an event generation unit for generating test vectors based on the event data where waveform of each vector is determined by the event type and a timing of the waveform is determined by accumulating the time index of previous events, and means for supplying test vectors to the DUT and evaluating response outputs of the DUT at predetermined timings.

Event based IC test system

An apparatus for supporting and manipulating a testhead for testing semiconductor devices includes a supporting frame, plates adapted to be mounted on opposite sides of the testhead and controllable shafts that connect the supporting frame to the plates. Each plate has an opening in which a flanged bearing is fitted. The testhead is mounted by moving the respective shafts through the flanged bearings within the openings of plates. In this manner, the shafts support the testhead on two fixed pivots. The shafts also provide a fixed axis of rotation about which the testhead can be rotated. The testhead can be locked in a particular position about the fixed rotation axis by a locking pin inserted into one of a plurality of locking holes surrounding the plate opening. A lever arm connected to the locking pin is utilized to change the radial position of the testhead. The testhead is dismounted by unlocking the locking pin and moving the shafts from the flanged bearings.

Apparatus for supporting and manipulating a testhead in an automatic test equipment system

The present invention is directed to a locking apparatus and loadboard assembly of a semiconductor testing device apparatus. The loadboard assembly includes a printed circuit board containing a device under test and an interface board secured to the bottom of the printed circuit board. The interface board has two members with a space between them. Spacers connect the members to form apertures for contact pins on a test head. The loadboard assembly is placed on top of a locking apparatus which is mounted on the top surface of the test head. The placement of the loadboard on the locking apparatus is done according to two pins of different cross-sections that extend through two holes in the interface board and printed circuit board of the loadboard assembly. When the loadboard assembly is placed on the locking mechanism, rollers mounted on the interface board are received in cam slots of a cam member of the locking apparatus. These rollers follow the cam slots as the cam member is moved. Based on the profile of the cam slots, the loadboard assembly can be gradually lowered to achieve contact between the printed circuit board and the contact pins on the test head and to lock the interface board.

Locking apparatus and loadboard assembly

The present invention is directed to a test head Hifix of a semiconductor device testing apparatus that does not require disassembly for maintenance or repair of the semiconductor device testing apparatus. In one embodiment, the test head Hifix of a semiconductor device testing apparatus includes a plate that resides as the top surface of a test head and on which the assembly, loadboard, socket and DUT are mounted. The plate is attached to the test head in an arrangement that allows the plate along with the assembly, loadboard, socket and DUT to be easily moved without completely disassembling the plate, assembly and loadboard from the test head. In one embodiment, the plate is attached or coupled to the test head by hinges.

Test head Hifix for semiconductor device testing apparatus

An emulator software in a semiconductor test system for emulating hardware in the semiconductor test system as well as a semiconductor device to be tested without need to use an actual test system hardware. The emulator software includes an emulator unit which emulates a function of each hardware unit of the test system, a device emulator which emulates a function of a semiconductor device to be tested, a data collecting part for acquiring data from the emulator unit necessary for carrying out a test program, and a device test emulator which generates a test signal to be applied to the device emulator based on the acquired data and compares the resultant signal from the device emulator with the expected data and stores the comparison result therein. In the other aspect, the emulator is combined with the operating system of the semiconductor test system which is capable of easily modifying the software when there is a change or replacement of the hardware of the test system so that the transmission of the control data for the hardware and its operation or the development of the test program can be carried out without using the hardware of the test system.

Test system emulator

A software structure in a semiconductor test system for easily modifying and transferring data for controlling a hardware when the hardware is changed or replaced. The semiconductor test system includes, an input for providing a test program for specifying various test conditions necessary to test the semiconductor device under test, a master processor for converting the test program to an object code and interpreting the contents of the test program, a processor interface for storing data indicating the hardware characteristics of the semiconductor test system in a table format to assist the interpretation of the test program in the master processor and modifying the table format data in response to the change in the hardware, a library having data tables based on the specification of the semiconductor test system for converting the format of the data compiled and interpreted by the master processor to data of a hardware format, and a driver for transmitting the hardware format data to registers in the hardware of the semiconductor test system through a data bus.

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Santa Clara, CA, United States of America

Robert F Sauer